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Date: Fri, 22 Apr 2022 14:01:46 +0800 From: Rex-BC Chen <rex-bc.chen@...iatek.com> To: <mturquette@...libre.com>, <sboyd@...nel.org>, <matthias.bgg@...il.com>, <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org> CC: <p.zabel@...gutronix.de>, <angelogioacchino.delregno@...labora.com>, <chun-jie.chen@...iatek.com>, <wenst@...omium.org>, <runyang.chen@...iatek.com>, <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-clk@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>, <Project_Global_Chrome_Upstream_Group@...iatek.com>, Rex-BC Chen <rex-bc.chen@...iatek.com> Subject: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock We will use the infra_ao reset which is defined in mt8192-sys-clock. The maximum value of reset-cells is 2. Therefore, we add this patch to define it. Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com> --- .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml index 5705bcf1fe47..28ebcecc8258 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml @@ -29,6 +29,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + maximum: 2 + required: - compatible - reg -- 2.18.0
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