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Message-Id: <165053012237.502660.4418683392126519698.b4-ty@kernel.org>
Date:   Fri, 22 Apr 2022 11:55:35 +0100
From:   Will Deacon <will@...nel.org>
To:     jonathanh@...dia.com, linux-arm-kernel@...ts.infradead.org,
        linux-tegra@...r.kernel.org, iommu@...ts.linux-foundation.org,
        thierry.reding@...il.com, vdumpa@...dia.com,
        Ashish Mhetre <amhetre@...dia.com>, joro@...tes.org,
        robin.murphy@....com, linux-kernel@...r.kernel.org
Cc:     catalin.marinas@....com, kernel-team@...roid.com,
        Will Deacon <will@...nel.org>, nicolinc@...dia.com,
        Snikam@...dia.com, Pritesh Raithatha <praithatha@...dia.com>
Subject: Re: [Patch v2] iommu: arm-smmu: disable large page mappings for Nvidia arm-smmu

On Thu, 21 Apr 2022 13:45:04 +0530, Ashish Mhetre wrote:
> Tegra194 and Tegra234 SoCs have the erratum that causes walk cache
> entries to not be invalidated correctly. The problem is that the walk
> cache index generated for IOVA is not same across translation and
> invalidation requests. This is leading to page faults when PMD entry is
> released during unmap and populated with new PTE table during subsequent
> map request. Disabling large page mappings avoids the release of PMD
> entry and avoid translations seeing stale PMD entry in walk cache.
> Fix this by limiting the page mappings to PAGE_SIZE for Tegra194 and
> Tegra234 devices. This is recommended fix from Tegra hardware design
> team.
> 
> [...]

Applied to will (for-joerg/arm-smmu/fixes), thanks!

[1/1] iommu: arm-smmu: disable large page mappings for Nvidia arm-smmu
      https://git.kernel.org/will/c/4a25f2ea0e03

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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