| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Fri, 22 Apr 2022 14:27:23 +0200
From: Oleksij Rempel <o.rempel@...gutronix.de>
To: alexandru.tachici@...log.com
Cc: andrew@...n.ch, davem@...emloft.net, devicetree@...r.kernel.org,
hkallweit1@...il.com, kuba@...nel.org,
linux-kernel@...r.kernel.org, linux@...linux.org.uk,
netdev@...r.kernel.org, robh+dt@...nel.org
Subject: Re: [PATCH v6 1/7] ethtool: Add 10base-T1L link mode entry
Hi Alexandru,
on top of kernel v5.18-rcX you will need following changes:
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 8406ac739def..7e18d1571f78 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -90,8 +90,9 @@ const int phy_10_100_features_array[4] = {
};
EXPORT_SYMBOL_GPL(phy_10_100_features_array);
-const int phy_basic_t1_features_array[2] = {
+const int phy_basic_t1_features_array[3] = {
ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
};
EXPORT_SYMBOL_GPL(phy_basic_t1_features_array);
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 06943889d747..2c5e45e2b1f3 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -168,8 +168,10 @@ static void phylink_caps_to_linkmodes(unsigned long *linkmodes,
if (caps & MAC_10HD)
__set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, linkmodes);
- if (caps & MAC_10FD)
+ if (caps & MAC_10FD) {
__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, linkmodes);
+ __set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, linkmodes);
+ }
if (caps & MAC_100HD) {
__set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, linkmodes);
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 36ca2b5c2253..b12af9e2f389 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -65,7 +65,7 @@ extern const int phy_basic_ports_array[3];
extern const int phy_fibre_port_array[1];
extern const int phy_all_ports_features_array[7];
extern const int phy_10_100_features_array[4];
-extern const int phy_basic_t1_features_array[2];
+extern const int phy_basic_t1_features_array[3];
extern const int phy_gbit_features_array[2];
extern const int phy_10gbit_features_array[1];
On Tue, Apr 12, 2022 at 04:07:00PM +0300, alexandru.tachici@...log.com wrote:
> From: Alexandru Tachici <alexandru.tachici@...log.com>
>
> Add entry for the 10base-T1L full duplex mode.
>
> Reviewed-by: Andrew Lunn <andrew@...n.ch>
> Reviewed-by: Oleksij Rempel <o.rempel@...gutronix.de>
> Signed-off-by: Alexandru Tachici <alexandru.tachici@...log.com>
> ---
> drivers/net/phy/phy-core.c | 3 ++-
> include/uapi/linux/ethtool.h | 1 +
> net/ethtool/common.c | 3 +++
> 3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
> index 2001f3329133..1f2531a1a876 100644
> --- a/drivers/net/phy/phy-core.c
> +++ b/drivers/net/phy/phy-core.c
> @@ -13,7 +13,7 @@
> */
> const char *phy_speed_to_str(int speed)
> {
> - BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
> + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 93,
> "Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
> "If a speed or mode has been added please update phy_speed_to_str "
> "and the PHY settings array.\n");
> @@ -176,6 +176,7 @@ static const struct phy_setting settings[] = {
> /* 10M */
> PHY_SETTING( 10, FULL, 10baseT_Full ),
> PHY_SETTING( 10, HALF, 10baseT_Half ),
> + PHY_SETTING( 10, FULL, 10baseT1L_Full ),
> };
> #undef PHY_SETTING
>
> diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
> index 7bc4b8def12c..e0f0ee9bc89e 100644
> --- a/include/uapi/linux/ethtool.h
> +++ b/include/uapi/linux/ethtool.h
> @@ -1691,6 +1691,7 @@ enum ethtool_link_mode_bit_indices {
> ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,
> ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
> ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
> + ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,
> /* must be last entry */
> __ETHTOOL_LINK_MODE_MASK_NBITS
> };
> diff --git a/net/ethtool/common.c b/net/ethtool/common.c
> index 0c5210015911..566adf85e658 100644
> --- a/net/ethtool/common.c
> +++ b/net/ethtool/common.c
> @@ -201,6 +201,7 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
> __DEFINE_LINK_MODE_NAME(400000, CR4, Full),
> __DEFINE_LINK_MODE_NAME(100, FX, Half),
> __DEFINE_LINK_MODE_NAME(100, FX, Full),
> + __DEFINE_LINK_MODE_NAME(10, T1L, Full),
> };
> static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
>
> @@ -236,6 +237,7 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
> #define __LINK_MODE_LANES_T1 1
> #define __LINK_MODE_LANES_X 1
> #define __LINK_MODE_LANES_FX 1
> +#define __LINK_MODE_LANES_T1L 1
>
> #define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex) \
> [ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = { \
> @@ -349,6 +351,7 @@ const struct link_mode_info link_mode_params[] = {
> __DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
> __DEFINE_LINK_MODE_PARAMS(100, FX, Half),
> __DEFINE_LINK_MODE_PARAMS(100, FX, Full),
> + __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
> };
> static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);
>
> --
> 2.25.1
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Powered by blists - more mailing lists