[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAK8P3a0E4=8Drn_x19MkauNL_WC4vEL6wqkDqrafbT-n8cZpDA@mail.gmail.com>
Date: Fri, 22 Apr 2022 15:20:11 +0200
From: Arnd Bergmann <arnd@...db.de>
To: "Hawkins, Nick" <nick.hawkins@....com>
Cc: "Verdun, Jean-Marie" <verdun@....com>,
Joel Stanley <joel@....id.au>, Arnd Bergmann <arnd@...db.de>,
OpenBMC Maillist <openbmc@...ts.ozlabs.org>,
Russell King <linux@...linux.org.uk>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 01/11] archh: arm: mach-hpe: Introduce the HPE GXP architecture
On Thu, Apr 21, 2022 at 9:21 PM <nick.hawkins@....com> wrote:
> +
> +DT_MACHINE_START(GXP_DT, "HPE GXP")
> + .dt_compat = gxp_board_dt_compat,
> + .l2c_aux_val = 0,
> + .l2c_aux_mask = 0,
> +MACHINE_END
Ther l2c initialization looks wrong here, where you are saying here is
that all the bits of the aux register must be set to zero.
I also see that you don't have a device node for the cache controller, so
this is probably not actually used, but in general there should be one with
the correct properties.
Arnd
Powered by blists - more mailing lists