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Message-Id: <20220422133803.989256-4-chris.obbard@collabora.com>
Date: Fri, 22 Apr 2022 14:38:03 +0100
From: Christopher Obbard <chris.obbard@...labora.com>
To: Ezequiel Garcia <ezequiel@...guardiasur.com.ar>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Heiko Stuebner <heiko@...ech.de>,
Johan Jonker <jbx6244@...il.com>,
Alex Bee <knaerzche@...il.com>,
Elaine Zhang <zhangqing@...k-chips.com>
Cc: linux-media@...r.kernel.org, linux-rockchip@...ts.infradead.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, kernel@...labora.com,
Christopher Obbard <chris.obbard@...labora.com>
Subject: [PATCH 3/3] arm64: dts: rockchip: Add vdec support for RK3328
The RK3328 has an vdec device with dedicated iommu.
Describe the device and required power-domains in the
devicetree.
Signed-off-by: Christopher Obbard <chris.obbard@...labora.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 +++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index f8ef149fedad..390e1e4a8fc9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -306,6 +306,10 @@ power-domain@...328_PD_HEVC {
};
power-domain@...328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
#power-domain-cells = <0>;
};
power-domain@...328_PD_VPU {
@@ -660,6 +664,25 @@ vpu_mmu: iommu@...50800 {
power-domains = <&power RK3328_PD_VPU>;
};
+ vdec: video-codec@...60000 {
+ compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
+ reg = <0x0 0xff360000 0x0 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
+ assigned-clock-rates = <400000000>, <400000000>, <300000000>;
+ resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>,
+ <&cru SRST_VDEC_CABAC>, <&cru SRST_VDEC_CORE>,
+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>;
+ reset-names = "video_a", "video_h", "video_cabac", "video_core",
+ "niu_a", "niu_h";
+ iommus = <&vdec_mmu>;
+ power-domains = <&power RK3328_PD_VIDEO>;
+ };
+
vdec_mmu: iommu@...60480 {
compatible = "rockchip,iommu";
reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
@@ -667,7 +690,7 @@ vdec_mmu: iommu@...60480 {
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3328_PD_VIDEO>;
};
vop: vop@...70000 {
--
2.34.1
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