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Message-ID: <13768c7c-41e4-e24a-b325-2f01eeb1883f@gmail.com>
Date: Fri, 22 Apr 2022 16:10:28 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
Rob Herring <robh+dt@...nel.org>
Cc: Project_Global_Chrome_Upstream_Group@...iatek.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
Chen-Yu Tsai <wenst@...omium.org>,
Ryder Lee <ryder.lee@...nel.org>,
Hui Liu <hui.liu@...iatek.com>
Subject: Re: [PATCH 1/1] arm64: dts: mt8192: Add spmi node
On 19/04/2022 08:32, Allen-KH Cheng wrote:
> Add spmi node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Applied, thanks
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a6da7b04b9d4..164fae36a3d8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -537,6 +537,21 @@
> assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> };
>
> + spmi: spmi@...27000 {
> + compatible = "mediatek,mt6873-spmi";
> + reg = <0 0x10027000 0 0x000e00>,
> + <0 0x10029000 0 0x000100>;
> + reg-names = "pmif", "spmimst";
> + clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> + <&infracfg CLK_INFRA_PMIC_TMR>,
> + <&topckgen CLK_TOP_SPMI_MST_SEL>;
> + clock-names = "pmif_sys_ck",
> + "pmif_tmr_ck",
> + "spmimst_clk_mux";
> + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> + };
> +
> scp_adsp: clock-controller@...20000 {
> compatible = "mediatek,mt8192-scp_adsp";
> reg = <0 0x10720000 0 0x1000>;
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