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Message-ID: <26c0caf1-4cfc-9c7d-ac51-180ba4501bf5@nvidia.com>
Date: Sat, 23 Apr 2022 20:41:39 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: Raul Tambre <raul@...bre.ee>, bhelgaas@...gle.com,
lorenzo.pieralisi@....com, robh+dt@...nel.org,
thierry.reding@...il.com, jonathanh@...dia.com
Cc: kishon@...com, vkoul@...nel.org, kw@...ux.com, krzk@...nel.org,
p.zabel@...gutronix.de, mperttunen@...dia.com,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, kthota@...dia.com,
mmaddireddy@...dia.com, sagar.tv@...il.com
Subject: Re: [PATCH V2 2/8] dt-bindings: PCI: tegra: Add device tree support
for Tegra234
On 4/23/2022 7:57 PM, Raul Tambre wrote:
> External email: Use caution opening links or attachments
>
>
> On 2022-04-23 15:48, Vidya Sagar wrote:
>> @@ -47,16 +64,33 @@ Required properties:
>> "p2u-N": where N ranges from 0 to one less than the total number
>> of lanes
>> - nvidia,bpmp: Must contain a pair of phandle to BPMP controller
>> node followed
>> by controller-id. Following are the controller ids for each
>> controller.
>> + Tegra194:
>> + ---------
>> 0: C0
>> 1: C1
>> 2: C2
>> 3: C3
>> 4: C4
>> 5: C5
>> + Tegra194:
>
> Should this be Tegra234?
Yes.
Oops... How did I miss this? My bad.
>
>> + ---------
>> + 0 : C0
>> + 1 : C1
>> + 2 : C2
>> + 3 : C3
>> + 4 : C4
>> + 5 : C5
>> + 6 : C6
>> + 7 : C7
>> + 8 : C8
>> + 9 : C9
>> + 10: C10
>
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