linux-kernel - [PATCH V3 1/2] EDAC/synopsys: Disable the error interrupt on Synopsys EDAC v3.x hardware

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20220424013345.7359-2-sherry.sun@nxp.com>
Date:   Sun, 24 Apr 2022 09:33:44 +0800
From:   Sherry Sun <sherry.sun@....com>
To:     michal.simek@...inx.com, bp@...en8.de,
        Shubhrajyoti.datta@...inx.com, mchehab@...nel.org,
        tony.luck@...el.com, james.morse@....com, rric@...nel.org
Cc:     linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-imx@....com
Subject: [PATCH V3 1/2] EDAC/synopsys: Disable the error interrupt on Synopsys EDAC v3.x hardware

v3.x Synopsys EDAC DDR doesn't have the QOS Interrupt register, change
to use the ECC Clear Register to disable the error interrupts.

Signed-off-by: Sherry Sun <sherry.sun@....com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@...inx.com>
Acked-by: Michal Simek <michal.simek@...inx.com>
---
Changes in V3:
1. Improve the patch title and commit message as Borislav suggested.
---
 drivers/edac/synopsys_edac.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 40b1abeca856..88a481043d4c 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -865,8 +865,11 @@ static void enable_intr(struct synps_edac_priv *priv)
 static void disable_intr(struct synps_edac_priv *priv)
 {
 	/* Disable UE/CE Interrupts */
-	writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
-			priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+		writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+	else
+		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
 }
 
 static int setup_irq(struct mem_ctl_info *mci,
-- 
2.17.1