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Message-Id: <20220425182249.2753690-2-robimarko@gmail.com>
Date: Mon, 25 Apr 2022 20:22:44 +0200
From: Robert Marko <robimarko@...il.com>
To: agross@...nel.org, bjorn.andersson@...aro.org,
mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, absahu@...eaurora.org,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Cc: Robert Marko <robimarko@...il.com>
Subject: [PATCH 2/7] clk: qcom: ipq8074: disable USB GDSC-s SW_COLLAPSE
Like in IPQ6018 Qualcomm intentionally disables the SW_COLLAPSE on the USB
GDSC-s in the downstream 5.4 kernel.
This could potentially be better handled by utilizing the GDSC driver, but
I am not familiar with it nor do I have datasheets.
Signed-off-by: Robert Marko <robimarko@...il.com>
---
drivers/clk/qcom/gcc-ipq8074.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 2ebd1462db78..65249a03a672 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4806,6 +4806,11 @@ static int gcc_ipq8074_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
+ /* Disable SW_COLLAPSE for USB0 GDSCR */
+ regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
+ /* Disable SW_COLLAPSE for USB1 GDSCR */
+ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
+
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
&nss_crypto_pll_config);
--
2.35.1
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