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Message-ID: <20220425141926.00004d2e@Huawei.com>
Date:   Mon, 25 Apr 2022 14:19:26 +0100
From:   Jonathan Cameron <Jonathan.Cameron@...wei.com>
To:     Qing Wang <wangqing@...o.com>
CC:     Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Sudeep Holla <sudeep.holla@....com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <vincent.guittot@...aro.org>,
        <dietmar.eggemann@....com>
Subject: Re: [PATCH V2 0/2] Add complex scheduler level for arm64

On Fri, 22 Apr 2022 04:51:24 -0700
Qing Wang <wangqing@...o.com> wrote:

> From: Wang Qing <wangqing@...o.com>
> 
> The DSU cluster supports blocks that are called complexes
> which contain up to two cores of the same type and some shared logic,
> which sharing some logic between the cores can make a complex area efficient.
>

Given the complex shares things like the SVE units (cortex a510)...

Why not handle this as SMT?

Seems like a blurred boundary between separate cores and SMT threads.
I think we need to express and potentially take advantage of knowledge
about what logic is being shared.

Jonathan

 
> Complex also can be considered as a shared cache group smaller
> than cluster.
> 
> This patch adds complex level for complexs by parsing cache topology
> form DT. It will directly benefit a lot of workload which loves more
> resources such as memory bandwidth, caches.
> 
> Note this patch only handle the DT case.
> 
> V2:
> fix commit log and loop more
> 
> wangqing (2):
>   arch_topology: support for describing cache topology from DT
>   arm64: Add complex scheduler level for arm64
> 
>  arch/arm64/Kconfig            | 13 ++++++++++
>  arch/arm64/kernel/smp.c       | 48 ++++++++++++++++++++++++++++++++++-
>  drivers/base/arch_topology.c  | 47 +++++++++++++++++++++++++++++++++-
>  include/linux/arch_topology.h |  3 +++
>  4 files changed, 109 insertions(+), 2 deletions(-)
> 

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