linux-kernel - [RFC/RFT v2 03/11] dt-bindings: phy: rockchip: add PCIe v3 constants

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Date:   Tue, 26 Apr 2022 15:21:31 +0200
From:   Frank Wunderlich <linux@...web.de>
To:     linux-rockchip@...ts.infradead.org
Cc:     Frank Wunderlich <frank-w@...lic-files.de>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Johan Jonker <jbx6244@...il.com>,
        Peter Geis <pgwipeout@...il.com>,
        Michael Riesch <michael.riesch@...fvision.net>,
        linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-phy@...ts.infradead.org
Subject: [RFC/RFT v2 03/11] dt-bindings: phy: rockchip: add PCIe v3 constants

From: Frank Wunderlich <frank-w@...lic-files.de>

Add constants that can be used in devicetree and driver for
PCIe v3 phy.

Signed-off-by: Frank Wunderlich <frank-w@...lic-files.de>
---
v2:
- new patch because splitting out this file
- rename file from snps to rockchip
---
 include/dt-bindings/phy/phy-rockchip-pcie3.h | 21 ++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 include/dt-bindings/phy/phy-rockchip-pcie3.h

diff --git a/include/dt-bindings/phy/phy-rockchip-pcie3.h b/include/dt-bindings/phy/phy-rockchip-pcie3.h
new file mode 100644
index 000000000000..93e57edd337d
--- /dev/null
+++ b/include/dt-bindings/phy/phy-rockchip-pcie3.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _DT_BINDINGS_PHY_ROCKCHIP_PCIE3
+#define _DT_BINDINGS_PHY_ROCKCHIP_PCIE3
+
+/*
+ * pcie30_phy_mode[2:0]
+ * bit2: aggregation
+ * bit1: bifurcation for port 1
+ * bit0: bifurcation for port 0
+ */
+#define PHY_MODE_PCIE_AGGREGATION 4	/* PCIe3x4 */
+#define PHY_MODE_PCIE_NANBNB	0	/* P1:PCIe3x2  +  P0:PCIe3x2 */
+#define PHY_MODE_PCIE_NANBBI	1	/* P1:PCIe3x2  +  P0:PCIe3x1*2 */
+#define PHY_MODE_PCIE_NABINB	2	/* P1:PCIe3x1*2 + P0:PCIe3x2 */
+#define PHY_MODE_PCIE_NABIBI	3	/* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
+
+#endif /* _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 */
-- 
2.25.1