linux-kernel - Re: [PATCH 1/2] MIPS: Octeon: fix CN6640 hang on XAUI init

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Date:   Tue, 26 Apr 2022 16:30:38 +0200
From:   Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To:     Stijn Tintel <stijn@...ux-ipv6.be>
Cc:     linux-mips@...r.kernel.org, rdunlap@...radead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] MIPS: Octeon: fix CN6640 hang on XAUI init

On Sun, Apr 03, 2022 at 05:59:49AM +0300, Stijn Tintel wrote:
> Some CN66XX series Octeon II chips seem to hang if a reset is issued on
> XAUI initialization. Avoid the hang by disabling the reset.
> 
> Tested on SNIC10E.
> 
> Signed-off-by: Stijn Tintel <stijn@...ux-ipv6.be>
> ---
>  arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
> index fea71a85bb29..a92632223497 100644
> --- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
> +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
> @@ -156,8 +156,9 @@ int __cvmx_helper_xaui_enable(int interface)
>  	xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
>  	xauiCtl.s.lo_pwr = 0;
>  
> -	/* Issuing a reset here seems to hang some CN68XX chips. */
> -	if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
> +	/* Issuing a reset here seems to hang some CN66XX/CN68XX chips. */
> +	if (!OCTEON_IS_MODEL(OCTEON_CN66XX) &&
> +	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
>  	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
>  		xauiCtl.s.reset = 1;
>  
> -- 
> 2.35.1

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]