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Date:   Tue, 26 Apr 2022 17:28:14 +0000
From:   "Hawkins, Nick" <nick.hawkins@....com>
To:     Paul Menzel <pmenzel@...gen.mpg.de>
CC:     "Verdun, Jean-Marie" <verdun@....com>,
        "joel@....id.au" <joel@....id.au>, "arnd@...db.de" <arnd@...db.de>,
        "openbmc@...ts.ozlabs.org" <openbmc@...ts.ozlabs.org>,
        Russell King <linux@...linux.org.uk>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v5 01/11] aach: arm: mach-hpe: Introduce the HPE GXP
 architecture



-----Original Message-----
From: Paul Menzel [mailto:pmenzel@...gen.mpg.de] 
Sent: Tuesday, April 26, 2022 3:26 AM
To: Hawkins, Nick <nick.hawkins@....com>
Cc: Verdun, Jean-Marie <verdun@....com>; joel@....id.au; arnd@...db.de; openbmc@...ts.ozlabs.org; Russell King <linux@...linux.org.uk>; linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 01/11] aach: arm: mach-hpe: Introduce the HPE GXP architecture


> Type in the prefix: s/aach/arch/. Looking at `git log --oneline arch/arm`, *ARM* or *arm* seems to be commonly used though.
I will correct this, I will also look in all other patches to make sure appropriate titles are being used.

> > The GXP is the HPE BMC SoC that is used in the majority of HPE 
> > Generation 10 servers. Traditionally the asic will last multiple 
> > generations of server before being replaced.

> Please mention what kind of documentation (datasheets, …) are available.

Currently there are none available. The only reference I can provide will be arm documentation.

> > In gxp.c we reset the EHCI controller early to boot the asic.

> Why does the EHCI controller need to be reset?
This functionality was moved into the boot loader. This message is stale and needs to be removed. It was necessary for the chip to boot.

> > Info about SoC:
> > 
> > HPE GXP is the name of the HPE Soc. This SoC is used to implement many 
> > BMC features at HPE. It supports ARMv7 architecture based on the 
> > Cortex A9 core. It is capable of using an AXI bus to which a memory 
> > controller is attached. It has multiple SPI interfaces to connect boot 
> > flash and BIOS flash. It uses a 10/100/1000 MAC for network 
> > connectivity. It has multiple i2c engines to drive connectivity with a 
> > host infrastructure. The initial patches enable the watchdog and timer 
> > enabling the host to be able to boot.

> Maybe doe that in separate commits?
Are you asking for me to have this paragraph in the other commits? Or perhaps not mention the other patches in this paragraph? 

> Please reflow the commit message for 75 characters per line.
I will verify all the lines are under 75 characters.

Thanks for the feedback,

-Nick Hawkins

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