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Message-ID: <CA+ASDXMkzrqkDdb=y4DpK5Ot=XFtj6aAv7-mSBoGP5rDJZanpA@mail.gmail.com>
Date: Tue, 26 Apr 2022 11:02:52 -0700
From: Brian Norris <briannorris@...omium.org>
To: Srinivasarao Pathipati <quic_spathi@...cinc.com>
Cc: Ulf Hansson <ulf.hansson@...aro.org>, avri.altman@....com,
Linus Walleij <linus.walleij@...aro.org>,
vbadigan@...eaurora.org, Shawn Lin <shawn.lin@...k-chips.com>,
s.shtylyov@....ru, merez@...eaurora.org,
wsa+renesas@...g-engineering.com, sayalil@...eaurora.org,
linux-mmc@...r.kernel.org,
Linux Kernel <linux-kernel@...r.kernel.org>,
Kishor Krishna Bhat <quic_kishkris@...cinc.com>,
kamasali <quic_kamasali@...cinc.com>
Subject: Re: [PATCH V1] mmc: core: Select HS mode in device first and then in
the host
Hi,
On Tue, Apr 26, 2022 at 2:16 AM Srinivasarao Pathipati
<quic_spathi@...cinc.com> wrote:
>
> From: Sayali Lokhande <sayalil@...eaurora.org>
>
> While switching from hs400 to hs200 mode, high speed mode
> timing should be selected in the device before changing the
> clock frequency in the host. But current implementation,
> (mmc_hs400_to_hs200) first updates the frequency in the host
> and then updates mode in the device. This is a spec violation.
> Hence update the sequence to comply with the spec.
I'm a bit new to interpreting eMMC specs, but are you sure this is a
violation? In JESD84-B51, I see:
"The bus frequency can be changed at any time (under the restrictions
of maximum data transfer frequency, defined by the Device, and the
identification frequency defined by the standard document)."
I think that suggests we can lower the host clock first, and then
lower the device timing. And (according to my limited knowledge) that
makes sense too: the device timing is a "maximum" (to some extent) and
we're free to run the host bus somewhat slower.
And on the flip side: it sounds like you may be _introducing_ a spec
violation (that we'll be running the host faster than the device
timing, briefly)?
Apologies if I'm off base. But you did CC me ;)
Regards,
Brian
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