linux-kernel - [PATCH V4 12/15] dt-bindings: reset: mediatek: Add infra

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Message-ID: <20220427030950.23395-13-rex-bc.chen@mediatek.com>
Date:   Wed, 27 Apr 2022 11:09:47 +0800
From:   Rex-BC Chen <rex-bc.chen@...iatek.com>
To:     <mturquette@...libre.com>, <sboyd@...nel.org>,
        <matthias.bgg@...il.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>
CC:     <p.zabel@...gutronix.de>,
        <angelogioacchino.delregno@...labora.com>,
        <chun-jie.chen@...iatek.com>, <wenst@...omium.org>,
        <runyang.chen@...iatek.com>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        Rex-BC Chen <rex-bc.chen@...iatek.com>
Subject: [PATCH V4 12/15] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192/MT8195

- To support reset of infra_ao, add the bit definition of
  thermal/PCIe/SVS for MT8192.
- To support reset of infra_ao, add the bit definition of
  thermal/SVS for MT8195.
- Add the driver comment to separate the reset index for
  TOPRGU and INFRA.

Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
---
 include/dt-bindings/reset/mt8192-resets.h | 8 ++++++++
 include/dt-bindings/reset/mt8195-resets.h | 6 ++++++
 2 files changed, 14 insertions(+)

diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
index be9a7ca245b9..ee0ca02a39bf 100644
--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h
@@ -7,6 +7,7 @@
 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
 #define _DT_BINDINGS_RESET_CONTROLLER_MT8192
 
+/* TOPRGU resets */
 #define MT8192_TOPRGU_MM_SW_RST					1
 #define MT8192_TOPRGU_MFG_SW_RST				2
 #define MT8192_TOPRGU_VENC_SW_RST				3
@@ -27,4 +28,11 @@
 
 #define MT8192_TOPRGU_SW_RST_NUM				23
 
+/* INFRA resets */
+#define MT8192_INFRA_THERMAL_CTRL_RST			0
+#define MT8192_INFRA_PEXTP_PHY_RST				79
+#define MT8192_INFRA_PTP_RST					101
+#define MT8192_INFRA_RST4_PCIE_TOP				129
+#define MT8192_INFRA_THERMAL_CTRL_MCU_RST		140
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..a3226f40779c 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -7,6 +7,7 @@
 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
 #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
 
+/* TOPRGU resets */
 #define MT8195_TOPRGU_CONN_MCU_SW_RST          0
 #define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
 #define MT8195_TOPRGU_APU_SW_RST               2
@@ -26,4 +27,9 @@
 
 #define MT8195_TOPRGU_SW_RST_NUM               16
 
+/* INFRA resets */
+#define MT8195_INFRA_THERMAL_AP_RST            0
+#define MT8195_INFRA_PTP_RST                   101
+#define MT8195_INFRA_THERMAL_MCU_RST           138
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
-- 
2.18.0