linux-kernel - [PATCH V4 1/2] EDAC/synopsys: Disable the error interrupt on Synopsys EDAC v3.x hardware

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Date:   Wed, 27 Apr 2022 09:51:36 +0800
From:   Sherry Sun <sherry.sun@....com>
To:     bp@...en8.de, michal.simek@...inx.com,
        Shubhrajyoti.datta@...inx.com, dinguyen@...nel.org
Cc:     linux-edac@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-imx@....com
Subject: [PATCH V4 1/2] EDAC/synopsys: Disable the error interrupt on Synopsys EDAC v3.x hardware

v3.x Synopsys EDAC DDR doesn't have the QOS Interrupt register, change
to use the ECC Clear Register to disable the error interrupts.

Fixes: f7824ded4149 ("EDAC/synopsys: Add support for version 3 of the Synopsys EDAC DDR")
Signed-off-by: Sherry Sun <sherry.sun@....com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@...inx.com>
Acked-by: Michal Simek <michal.simek@...inx.com>
---
Changes in V4:
1. Add Fixes tag.
---
 drivers/edac/synopsys_edac.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 40b1abeca856..88a481043d4c 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -865,8 +865,11 @@ static void enable_intr(struct synps_edac_priv *priv)
 static void disable_intr(struct synps_edac_priv *priv)
 {
 	/* Disable UE/CE Interrupts */
-	writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
-			priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+		writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+	else
+		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
 }
 
 static int setup_irq(struct mem_ctl_info *mci,
-- 
2.17.1