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Date: Thu, 28 Apr 2022 17:35:56 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: "Srikandan, Nandhini" <nandhini.srikandan@...el.com>
Cc: Serge Semin <Sergey.Semin@...kalelectronics.ru>,
"broonie@...nel.org" <broonie@...nel.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"mgross@...ux.intel.com" <mgross@...ux.intel.com>,
"Pan, Kris" <kris.pan@...el.com>,
"Demakkanavar, Kenchappa" <kenchappa.demakkanavar@...el.com>,
"Zhou, Furong" <furong.zhou@...el.com>,
"Sangannavar, Mallikarjunappa"
<mallikarjunappa.sangannavar@...el.com>,
"Vaidya, Mahesh R" <mahesh.r.vaidya@...el.com>,
"A, Rashmi" <rashmi.a@...el.com>
Subject: Re: [PATCH v4 3/3] spi: dw: Add support for master mode selection
for DWC SSI controller
On Wed, Apr 27, 2022 at 09:51:47AM +0000, Srikandan, Nandhini wrote:
>
>
> > -----Original Message-----
> > From: Serge Semin <fancer.lancer@...il.com>
> > Sent: Wednesday, April 13, 2022 6:33 PM
> > To: Srikandan, Nandhini <nandhini.srikandan@...el.com>
> > Cc: Serge Semin <Sergey.Semin@...kalelectronics.ru>; broonie@...nel.org;
> > robh+dt@...nel.org; linux-spi@...r.kernel.org; linux-
> > kernel@...r.kernel.org; devicetree@...r.kernel.org;
> > mgross@...ux.intel.com; Pan, Kris <kris.pan@...el.com>; Demakkanavar,
> > Kenchappa <kenchappa.demakkanavar@...el.com>; Zhou, Furong
> > <furong.zhou@...el.com>; Sangannavar, Mallikarjunappa
> > <mallikarjunappa.sangannavar@...el.com>; Vaidya, Mahesh R
> > <mahesh.r.vaidya@...el.com>; A, Rashmi <rashmi.a@...el.com>
> > Subject: Re: [PATCH v4 3/3] spi: dw: Add support for master mode selection
> > for DWC SSI controller
> >
> > Hello Nandhini
> >
> > AFAICS this patch should go before
> > [PATCH v4 2/3] spi: dw: Add support for Intel Thunder Bay SPI controller
> > Thus you'd perform the DWC AHB SSI Master mode conversion first, then
> > introduce the new controller support. Otherwise without this patch applied
> > the DW SPI driver is most likely left broken for the Intel SPI controllers since
> > you drop the DW_SPI_CAP_KEEMBAY_MST macro usage in [PATCH 2/3] while
> > the new DW AHB SSI Master functionality is introduced in the next patch
> > [PATCH 3/3]. So please convert the series to the harmless configuration on
> > each git image state.
> >
> Sure, I will reorder patch 2/3 and 3/3 so that the master mode conversion happens first followed by new controller support.
>
> > On Tue, Mar 08, 2022 at 06:33:31PM +0800, nandhini.srikandan@...el.com
> > wrote:
> > > From: Nandhini Srikandan <nandhini.srikandan@...el.com>
> > >
> > > Add support to select the controller mode as master mode by setting
> > > Bit 31 of CTRLR0 register. This feature is supported for controller
> > > versions above v1.02.
> > >
> > > Signed-off-by: Nandhini Srikandan <nandhini.srikandan@...el.com>
> > > ---
> > > drivers/spi/spi-dw-core.c | 4 ++--
> > > drivers/spi/spi-dw.h | 7 +++----
> > > 2 files changed, 5 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
> > > index ecea471ff42c..68bfdf2c4dc7 100644
> > > --- a/drivers/spi/spi-dw-core.c
> > > +++ b/drivers/spi/spi-dw-core.c
> > > @@ -307,8 +307,8 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws,
> > struct spi_device *spi)
> > > if (spi->mode & SPI_LOOP)
> > > cr0 |= DW_HSSI_CTRLR0_SRL;
> > >
> >
> > > - if (dws->caps & DW_SPI_CAP_KEEMBAY_MST)
> > > - cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST;
> > > + /* CTRLR0[31] MST */
> > > + cr0 |= DW_HSSI_CTRLR0_MST;
> >
> > Could you please conditionally set that flag here? That's what we agreed to
> > do in v3:
> > https://lore.kernel.org/linux-
> > spi/20211116191542.vc42cxvflzn66ien@...ilestation/
> > like this:
> > + /* CTRLR0[31] MST */
> > + if (dw_spi_ver_is_ge(dws, HSSI, 102A))
> > + cr0 |= DWC_HSSI_CTRLR0_MST;
> >
> In case of Keem Bay, though the version of SPI controller is shown as 1.01a from the HW register, it still needs the MST BIT31 to be set in order for controller to work in master mode.
> Also since the older versions of the controller which do not need the BIT31 to be set, the bit was reserved. Hence there is no impact by setting this BIT31 for older versions.
> So, the condition check was removed.
I am completely confused. Earlier you said that both Keem Bay and
Thunder bay had v1.02a DW AHB SSI IP-core:
https://patchwork.kernel.org/project/spi-devel-general/patch/20210824085856.12714-3-nandhini.srikandan@intel.com/
Now you say they are based on the different versions of the core.
Please clarify.
-Sergey
>
> > > }
> > >
> > > return cr0;
> > > diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index
> > > d5ee5130601e..2583b7314c41 100644
> > > --- a/drivers/spi/spi-dw.h
> > > +++ b/drivers/spi/spi-dw.h
> > > @@ -23,7 +23,7 @@
> > > ((_dws)->ip == DW_ ## _ip ## _ID)
> > >
> >
> > > #define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \
> > > - (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ver)
> > > + (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ##
> > _ver)
> >
> > Nice catch. My mistake. Could you please move this change into a dedicated
> > patch with the next fixes tag?
> > Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions
> > interface")
> >
> Sure, I will convert this to a dedicated patch. Just for confirmation, the patch should be a separate patch with this title "Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions interface")"
> and not part of the current patch set series.
You can add that patch to this series (better to the head of it). The
title can be something like: "spi: dw: Fix IP-core versions macro".
The tag needs to be added in the commit log above the Signed-off-by
tag.
-Sergey
> > >
> > > #define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip,
> > > _ver, ==)
> > >
> > > @@ -31,8 +31,7 @@
> > >
> > > /* DW SPI controller capabilities */
> > > #define DW_SPI_CAP_CS_OVERRIDE BIT(0)
> > > -#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
> > > -#define DW_SPI_CAP_DFS32 BIT(2)
> > > +#define DW_SPI_CAP_DFS32 BIT(1)
> > >
> > > /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
> > > #define DW_SPI_CTRLR0 0x00
> > > @@ -100,7 +99,7 @@
> >
> > > * 0: SSI is slave
> > > * 1: SSI is master
> > > */
> > > -#define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31)
> > > +#define DW_HSSI_CTRLR0_MST BIT(31)
> >
> > Could you please drop the redundant comment above and join the macro
> > with the DW_HSSI_* macros group?
> >
> Sure, I will remove the comment and group the macros.
> > -Sergey
> >
> > >
> > > /* Bit fields in CTRLR1 */
> > > #define DW_SPI_NDF_MASK GENMASK(15, 0)
> > > --
> > > 2.17.1
> > >
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