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Message-Id: <20220428151630.586009-3-herve.codina@bootlin.com>
Date: Thu, 28 Apr 2022 17:16:26 +0200
From: Herve Codina <herve.codina@...tlin.com>
To: Marek Vasut <marek.vasut+renesas@...il.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Krzysztof WilczyĆski <kw@...ux.com>
Cc: Rob Herring <robh@...nel.org>, linux-pci@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Sergey Shtylyov <s.shtylyov@....ru>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Clement Leger <clement.leger@...tlin.com>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Herve Codina <herve.codina@...tlin.com>
Subject: [PATCH v4 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032
Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of
one.
The 'resets' property for the RZ/N1 family is not required since
there is no reset-controller support yet for the RZ/N1 family.
Signed-off-by: Herve Codina <herve.codina@...tlin.com>
---
.../bindings/pci/renesas,pci-rcar-gen2.yaml | 46 ++++++++++++++++---
1 file changed, 39 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
index 494eb975c146..90b42d44c582 100644
--- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
@@ -32,6 +32,10 @@ properties:
- renesas,pci-r8a7793 # R-Car M2-N
- renesas,pci-r8a7794 # R-Car E2
- const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+ - items:
+ - enum:
+ - renesas,pci-r9a06g032 # RZ/N1D
+ - const: renesas,pci-rzn1 # RZ/N1
reg:
items:
@@ -41,13 +45,9 @@ properties:
interrupts:
maxItems: 1
- clocks:
- items:
- - description: Device clock
+ clocks: true
- clock-names:
- items:
- - const: pclk
+ clock-names: true
resets:
maxItems: 1
@@ -106,13 +106,45 @@ required:
- interrupt-map
- interrupt-map-mask
- clocks
- - resets
- power-domains
- bus-range
- "#address-cells"
- "#size-cells"
- "#interrupt-cells"
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,pci-rzn1
+
+then:
+ properties:
+ clocks:
+ items:
+ - description: Internal bus clock (AHB) for HOST
+ - description: Internal bus clock (AHB) Power Management
+ - description: PCI clock for USB subsystem
+ clock-names:
+ items:
+ - const: usb_hclkh
+ - const: usb_hclkpm
+ - const: usb_pciclk
+ required:
+ - clock-names
+
+else:
+ properties:
+ clocks:
+ items:
+ - description: Device clock
+ clock-names:
+ items:
+ - const: pclk
+ required:
+ - resets
+
unevaluatedProperties: false
examples:
--
2.35.1
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