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Message-ID: <79b2bdef-37b5-9b15-3739-5281d4bc8c9e@collabora.com>
Date: Thu, 28 Apr 2022 15:38:16 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Rex-BC Chen <rex-bc.chen@...iatek.com>, mturquette@...libre.com,
sboyd@...nel.org, matthias.bgg@...il.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org
Cc: p.zabel@...gutronix.de, chun-jie.chen@...iatek.com,
wenst@...omium.org, runyang.chen@...iatek.com,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH V5 07/16] clk: mediatek: reset: Support nonsequence base
offsets of reset registers
Il 28/04/22 13:56, Rex-BC Chen ha scritto:
> The bank offsets are not serial for all reset registers.
> For example, there are five infra reset banks for MT8192: 0x120, 0x130,
> 0x140, 0x150 and 0x730.
>
> To support this,
> - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of
> the reset register.
> - Add a new define RST_NR_PER_BANK to define reset number for each
> reset bank.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
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