linux-kernel - Re: [PATCH v4 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling

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Message-ID: <3f799406-25f0-3105-250b-dfc68cac263f@amd.com>
Date:   Fri, 29 Apr 2022 10:40:39 +0530
From:   Sandipan Das <sandipan.das@....com>
To:     Like Xu <like.xu.linux@...il.com>
Cc:     peterz@...radead.org, bp@...en8.de, dave.hansen@...ux.intel.com,
        acme@...nel.org, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, namhyung@...nel.org,
        jolsa@...nel.org, tglx@...utronix.de, mingo@...hat.com,
        pbonzini@...hat.com, jmattson@...gle.com, eranian@...gle.com,
        puwen@...on.cn, ananth.narayan@....com, ravi.bangoria@....com,
        santosh.shukla@....com,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-perf-users@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH v4 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling


On 4/28/2022 7:10 PM, Like Xu wrote:
> On 27/4/2022 7:31 pm, Sandipan Das wrote:
>> +static inline void amd_pmu_ack_global_status(u64 status)
>> +{
>> +    /*
>> +     * PerfCntrGlobalStatus is read-only but an overflow acknowledgment
> 
> If wrmsrl PerfCntrGlobalStatus, remain silent or report #GP ?
> 

This is a read-only MSR and writes are silently ignored.

>> +     * mechanism exists; writing 1 to a bit in PerfCntrGlobalStatusClr
>> +     * clears the same bit in PerfCntrGlobalStatus
>> +     */
>> +
>> +    /* Only allow modifications to PerfCntrGlobalStatus.PerfCntrOvfl */
>> +    status &= amd_pmu_global_cntr_mask;
>> +    wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, status);
> 
> If rdmsrl PerfCntrGlobalStatusClr, does it return 0 or the value of PerfCntrGlobalStatus ?
> 

This is a write-only MSR and reads are undefined.

The "Field Access Type" section from the AMD Processor Programming
Reference (PPR) has these details.


- Sandipan