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Message-ID: <20220429055833.ahgioqdjwgshpylk@ti.com>
Date: Fri, 29 Apr 2022 11:28:33 +0530
From: Pratyush Yadav <p.yadav@...com>
To: Ian Abbott <abbotti@....co.uk>
CC: <linux-spi@...r.kernel.org>, Mark Brown <broonie@...nel.org>,
Dinh Nguyen <dinguyen@...nel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] spi: cadence-quadspi: fix Direct Access Mode disable for
SoCFPGA
On 27/04/22 04:34PM, Ian Abbott wrote:
> The Cadence QSPI compatible string required for the SoCFPGA platform
> changed from the default "cdns,qspi-nor" to "intel,socfpga-qspi" with
> the introduction of an additional quirk in
> commit 98d948eb8331 ("spi: cadence-quadspi: fix write completion support").
> However, that change did not preserve the previously used
> quirk for this platform. Reinstate the `CQSPI_DISABLE_DAC_MODE` quirk
> for the SoCFPGA platform.
>
> Fixes: 98d948eb8331 ("spi: cadence-quadspi: fix write completion support")
> Cc: Dinh Nguyen <dinguyen@...nel.org>
> Signed-off-by: Ian Abbott <abbotti@....co.uk>
Reviewed-by: Pratyush Yadav <p.yadav@...com>
> ---
> drivers/spi/spi-cadence-quadspi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
> index 41922a5ea1f4..30307392c75a 100644
> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -1781,7 +1781,7 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = {
> };
>
> static const struct cqspi_driver_platdata socfpga_qspi = {
> - .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION,
> + .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION,
> };
>
> static const struct cqspi_driver_platdata versal_ospi = {
> --
> 2.35.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
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