linux-kernel - Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAMuHMdVARiVpch12HOMy8WR5pMnvVK-Mys8ZRnNK2u+y+qozJg@mail.gmail.com>
Date:   Fri, 29 Apr 2022 10:44:32 +0200
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Marc Zyngier <maz@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Renesas RZ/G2L
 Interrupt Controller

Hi Prabhakar,

On Fri, Apr 29, 2022 at 10:38 AM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
> On Thu, Apr 28, 2022 at 10:32 AM Geert Uytterhoeven
> > On Fri, Apr 22, 2022 at 12:12 AM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > > Add DT bindings for the Renesas RZ/G2L Interrupt Controller.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > @@ -0,0 +1,131 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
> > > +
> > > +maintainers:
> > > +  - Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > +  - Geert Uytterhoeven <geert+renesas@...der.be>
> > > +
> > > +description: |
> > > +  IA55 performs various interrupt controls including synchronization for the external
> > > +  interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
> > > +  interrupts output by each IP. And it notifies the interrupt to the GIC
> > > +    - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
> > > +    - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
> > > +    - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> > > +      stand-up edge detection interrupts)
> > > +
> > > +allOf:
> > > +  - $ref: /schemas/interrupt-controller.yaml#
> > > +
> > > +properties:
> > > +  compatible:
> > > +    items:
> > > +      - enum:
> > > +          - renesas,r9a07g044-irqc    # RZ/G2L
> > > +      - const: renesas,rzg2l-irqc
> > > +
> > > +  '#interrupt-cells':
> > > +    const: 2
> >
> > What is the meaning of the cells? IRQ number + flags, I assume?
> IRQ number and the type.
>
> > How are the numbers mapped, do you need a DT bindings header?
> No, just plain numbers are used (driver handles the validation of the
> interrupt numbering), for example like below,
>
> &eth0 {
>    ...
>    status = "okay";
>
>    phy0: ethernet-phy@7 {
>      compatible = "ethernet-phy-id0022.1640",
>                            "ethernet-phy-ieee802.3-c22";
>      reg = <7>;
>      interrupt-parent = <&irqc>;
>      interrupts = <3 IRQ_TYPE_LEVEL_LOW>;

OK, so the number must be an external interrupt number (0..7).

>     ...
>   };
> };
>
> And for the GPIO:
>
> key-1 {
>       gpios = <&pinctrl RZG2L_GPIO(43, 0) GPIO_ACTIVE_HIGH>;
>       linux,code = <KEY_1>;
>       linux,input-type = <EV_KEY>;
>       wakeup-source;
>       label = "SW1";
> };

OK, so in this case the interrupt number is obtained implicitly, and
no interrupts property is used.

> > Perhaps it would make sense to increase to 3 cells, so you can use
> > one cell for the type (cfr. e.g. GIC_SPI), and the second for the
> > plain index within the type?
> >
> Could you please elaborate on this. Are you referring to the type here
> as the type to be set up in the GIC?

Please ignore, you don't need the type, as it's always an external
interrupt number, right?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds