[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <YmvafYwhtIoaOMmk@lunn.ch>
Date: Fri, 29 Apr 2022 14:30:53 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Pali Rohár <pali@...nel.org>
Cc: Gregory Clement <gregory.clement@...tlin.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] irqchip/armada-370-xp: Do not allow mapping IRQ 0
and 1
On Mon, Apr 25, 2022 at 01:37:06PM +0200, Pali Rohár wrote:
> IRQs 0 and 1 cannot be mapped, they are handled internally by this driver
> and this driver does not call generic_handle_domain_irq() for these IRQs.
> So do not allow mapping these IRQs and correctly propagate error from the
> .irq_map callback.
So you are referring to this?
/* Check if the interrupt is not masked on current CPU.
* Test IRQ (0-1) and FIQ (8-9) mask bits.
*/
if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
continue;
if (irqn == 1) {
armada_370_xp_handle_msi_irq(NULL, true);
continue;
}
Should the two FIQ interrupts also return -EINVAL?
Andrew
Powered by blists - more mailing lists