linux-kernel - Re: [PATCH] arm64: dts: mt7622: specify the L2 cache topology

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Message-ID: <a9300186-07f8-30c4-b5d8-e88f6f0ee629@gmail.com>
Date:   Fri, 29 Apr 2022 14:58:25 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Rui Salvaterra <rsalvaterra@...il.com>,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc:     ryder.lee@...iatek.com, daniel@...rotopia.org
Subject: Re: [PATCH] arm64: dts: mt7622: specify the L2 cache topology



On 29/04/2022 00:57, Rui Salvaterra wrote:
> On an MT7622 system, the kernel complains of not being able to detect the cache
> hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
> order to fix this.
> 
> Signed-off-by: Rui Salvaterra <rsalvaterra@...il.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> index 6f8cb3ad1e84..3d6eaf6dd078 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -80,6 +80,7 @@ cpu0: cpu@0 {
>   			enable-method = "psci";
>   			clock-frequency = <1300000000>;
>   			cci-control-port = <&cci_control2>;
> +			next-level-cache = <&L2>;
>   		};
>   
>   		cpu1: cpu@1 {
> @@ -94,6 +95,12 @@ cpu1: cpu@1 {
>   			enable-method = "psci";
>   			clock-frequency = <1300000000>;
>   			cci-control-port = <&cci_control2>;
> +			next-level-cache = <&L2>;
> +		};
> +
> +		L2: l2-cache {
> +			compatible = "cache";
> +			cache-level = <2>;
>   		};
>   	};
>