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Message-Id: <20220430130922.3504268-9-mail@conchuod.ie>
Date: Sat, 30 Apr 2022 14:09:23 +0100
From: Conor Dooley <mail@...chuod.ie>
To: krzk+dt@...nel.org, palmer@...belt.com, robh+dt@...nel.org
Cc: conor.dooley@...rochip.com, Cyril.Jean@...rochip.com,
daire.mcnamara@...rochip.com, paul.walmsley@...ive.com,
aou@...s.berkeley.edu, palmer@...osinc.com, arnd@...db.de,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, Conor Dooley <mail@...chuod.ie>
Subject: [PATCH v2 8/8] riscv: dts: microchip: add the sundance polarberry
From: Conor Dooley <conor.dooley@...rochip.com>
Add a minimal device tree for the PolarFire SoC based Sundance
PolarBerry.
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Conor Dooley <mail@...chuod.ie>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++
.../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++
3 files changed, 112 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index af3a5059b350..39aae7b04f1c 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
new file mode 100644
index 000000000000..49380c428ec9
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/ {
+ fabric_clk3: fabric-clk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ };
+
+ fabric_clk1: fabric-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
new file mode 100644
index 000000000000..96ec589d1571
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-polarberry-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ 1000000
+
+/ {
+ model = "Sundance PolarBerry";
+ compatible = "sundance,polarberry", "microchip,mpfs";
+
+ aliases {
+ serial0 = &mmuart0;
+ ethernet0 = &mac1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <MTIMER_FREQ>;
+ };
+
+ ddrc_cache_lo: memory@...00000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x2e000000>;
+ status = "okay";
+ };
+
+ ddrc_cache_hi: memory@...0000000 {
+ device_type = "memory";
+ reg = <0x10 0x00000000 0x0 0xC0000000>;
+ status = "okay";
+ };
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&mmuart0 {
+ status = "okay";
+};
+
+&mmc {
+ status = "okay";
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+};
+
+&mac1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@5 {
+ reg = <5>;
+ ti,fifo-depth = <0x01>;
+ };
+ phy0: ethernet-phy@4 {
+ reg = <4>;
+ ti,fifo-depth = <0x01>;
+ };
+};
+
+&mac0 {
+ status = "disabled";
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&mbox {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
--
2.36.0
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