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Message-Id: <20220501192557.2631936-1-mail@conchuod.ie>
Date: Sun, 1 May 2022 20:25:50 +0100
From: Conor Dooley <mail@...chuod.ie>
To: krzk+dt@...nel.org, palmer@...belt.com, robh+dt@...nel.org
Cc: conor.dooley@...rochip.com, Cyril.Jean@...rochip.com,
daire.mcnamara@...rochip.com, paul.walmsley@...ive.com,
aou@...s.berkeley.edu, palmer@...osinc.com, arnd@...db.de,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, Conor Dooley <mail@...chuod.ie>
Subject: [PATCH v3 0/8] PolarFire SoC dt for 5.19
Hey all,
Got a few PolarFire SoC device tree related changes here for 5.19.
Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
compared to that submission, figured it would just be easier to keep
all the changes in one series.
As discussed on irc, patch 3 removes the duplicated "microchip" from
the device tree files so that they follow a soc-board.dts & a
soc{,-fabric}.dtsi format.
Patch 5 makes the fabric dtsi board specific by renaming the file to
mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
mpfs.dtsi. Additionally this will allow other boards to define their
own reference fabric design. A revision specific compatible, added in
patch 4, is added to the dt also.
The remainder of the series adds a bare minimum devicetree for the
Sundance Polarberry.
Thanks,
Conor.
Changes since v2:
- make ,icicle-reference compatible with ,mpfs & put it inside the enum
Changes since v1:
- fixed whitespace problems in the polarberry dts
- disabled mac0 for the polarberry as its port is on the optional
carrier board
[0] - https://lore.kernel.org/linux-riscv/20220425104521.132538-1-conor.dooley@microchip.com/
Conor Dooley (8):
riscv: dts: microchip: remove icicle memory clocks
riscv: dts: microchip: move sysctrlr out of soc bus
riscv: dts: microchip: remove soc vendor from filenames
dt-bindings: riscv: microchip: document icicle reference design
riscv: dts: microchip: make the fabric dtsi board specific
dt-bindings: vendor-prefixes: add Sundance DSP
dt-bindings: riscv: microchip: add polarberry compatible string
riscv: dts: microchip: add the sundance polarberry
.../devicetree/bindings/riscv/microchip.yaml | 3 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/riscv/boot/dts/microchip/Makefile | 3 +-
...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 +
...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 5 +-
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++
.../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++
.../{microchip-mpfs.dtsi => mpfs.dtsi} | 11 +--
8 files changed, 127 insertions(+), 10 deletions(-)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)
base-commit: a91b05f6b928e8fab750fc953d7df0aa6dc43547
--
2.36.0
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