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Date: Mon, 2 May 2022 07:14:36 -0700 From: Kaushal Kumar <quic_kaushalk@...cinc.com> To: <agross@...nel.org>, <bjorn.andersson@...aro.org>, <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org> CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <manivannan.sadhasivam@...aro.org>, "Kaushal Kumar" <quic_kaushalk@...cinc.com> Subject: [PATCH v2 2/4] ARM: dts: qcom: sdx65: Add QPIC NAND support Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX65 platform. Since there is no "aon" clock in SDX65, a dummy clock is provided. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org> Signed-off-by: Kaushal Kumar <quic_kaushalk@...cinc.com> --- arch/arm/boot/dts/qcom-sdx65.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index d6a6087..a75e9f1 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -37,6 +37,12 @@ clock-output-names = "sleep_clk"; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -211,6 +217,22 @@ status = "disabled"; }; + qpic_nand: nand-controller@...0000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + tcsr_mutex: hwlock@...0000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; -- 2.7.4
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