lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Tue, 3 May 2022 17:38:52 +0800 From: Rex-BC Chen <rex-bc.chen@...iatek.com> To: <mturquette@...libre.com>, <sboyd@...nel.org>, <matthias.bgg@...il.com>, <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org> CC: <p.zabel@...gutronix.de>, <angelogioacchino.delregno@...labora.com>, <chun-jie.chen@...iatek.com>, <wenst@...omium.org>, <runyang.chen@...iatek.com>, <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-clk@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>, <Project_Global_Chrome_Upstream_Group@...iatek.com>, Rex-BC Chen <rex-bc.chen@...iatek.com> Subject: [PATCH v6 12/16] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 We will use the infra_ao reset which is defined in mt8192-sys-clock and mt8195-sys-clock. The value of reset-cells is 1. Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> --- .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml | 3 +++ .../bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml | 3 +++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml index 5705bcf1fe47..27f79175c678 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml @@ -29,6 +29,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml index 57a1503d95fe..95b6bdf99936 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml @@ -37,6 +37,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg -- 2.18.0
Powered by blists - more mailing lists