lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 4 May 2022 06:43:15 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <heiko@...ech.de>, <krzk+dt@...nel.org>, <palmer@...belt.com>,
        <robh+dt@...nel.org>, <linux-riscv@...ts.infradead.org>
CC:     <Cyril.Jean@...rochip.com>, <Daire.McNamara@...rochip.com>,
        <paul.walmsley@...ive.com>, <aou@...s.berkeley.edu>,
        <palmer@...osinc.com>, <arnd@...db.de>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <robh@...nel.org>, <mail@...chuod.ie>
Subject: Re: [PATCH v3 2/8] riscv: dts: microchip: move sysctrlr out of soc
 bus

On 04/05/2022 00:37, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am Sonntag, 1. Mai 2022, 21:25:53 CEST schrieb Conor Dooley:
>> From: Conor Dooley <conor.dooley@...rochip.com>
>>
>> The MPFS system controller has no registers of its own, so move it out
>> of the soc node to avoid dtbs_check warnings:
>> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'}
>>
>> Reported-by: Palmer Dabbelt <palmer@...osinc.com>
>> Suggested-by: Rob Herring <robh@...nel.org>
>> Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
>> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> 
> What function does the "soc-bus" have at all?
> I.e. mailbox@...20000 also looks like a peripheral
> of the chip but is outside it.

I am not sure why a soc bus was chosen originally, splitting between
axi and ahb would be more accurate.

> 
> And I remember getting the suggestion to not use soc-"busses"
> over in arm-land years ago [0].
> 
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c3030d30d9c99c057b5ddfa289cffa637a2775f5
> 
>> ---
>>   arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++-----
>>   1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> index 746c4d4e7686..bf21a2edd180 100644
>> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> @@ -146,6 +146,11 @@ refclk: mssrefclk {
>>                #clock-cells = <0>;
>>        };
>>
>> +     syscontroller: syscontroller {
>> +             compatible = "microchip,mpfs-sys-controller";
>> +             mboxes = <&mbox 0>;
>> +     };
>> +
>>        soc {
>>                #address-cells = <2>;
>>                #size-cells = <2>;
>> @@ -446,10 +451,5 @@ mbox: mailbox@...20000 {
>>                        #mbox-cells = <1>;
>>                        status = "disabled";
>>                };
>> -
>> -             syscontroller: syscontroller {
>> -                     compatible = "microchip,mpfs-sys-controller";
>> -                     mboxes = <&mbox 0>;
>> -             };
>>        };
>>   };
>>
> 
> 
> 
> 

Powered by blists - more mailing lists