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Message-Id: <20220504142058.18704-1-wanjiabing@vivo.com>
Date: Wed, 4 May 2022 22:20:57 +0800
From: Wan Jiabing <wanjiabing@...o.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Biju Das <biju.das.jz@...renesas.com>,
linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: kael_w@...h.net, Wan Jiabing <wanjiabing@...o.com>
Subject: [PATCH] clk: renesas: rzg2l: Fix duplicate argument in rzg2l-cpg
Fix following coccicheck warning:
./drivers/clk/renesas/rzg2l-cpg.c:603:39-65: duplicated argument to & or |
The CPG_SIPLL5_CLK1_REFDIV_WEN here is duplicated.
Here should be CPG_SIPLL5_CLK1_POSTDIV2_WEN.
Fixes: a16ed737e62b ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
Signed-off-by: Wan Jiabing <wanjiabing@...o.com>
---
drivers/clk/renesas/rzg2l-cpg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 15412cc58337..a1e1fee9f483 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -600,7 +600,7 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
}
/* Output clock setting 1 */
- writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_REFDIV_WEN |
+ writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_POSTDIV2_WEN |
CPG_SIPLL5_CLK1_REFDIV_WEN | (params.pl5_postdiv1 << 0) |
(params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8),
priv->base + CPG_SIPLL5_CLK1);
--
2.35.1
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