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Date: Thu, 5 May 2022 08:46:53 +0000
From: "Tian, Kevin" <kevin.tian@...el.com>
To: Lu Baolu <baolu.lu@...ux.intel.com>,
Joerg Roedel <joro@...tes.org>,
Jason Gunthorpe <jgg@...dia.com>,
Alex Williamson <alex.williamson@...hat.com>
CC: "Pan, Jacob jun" <jacob.jun.pan@...el.com>,
"Liu, Yi L" <yi.l.liu@...el.com>,
"iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 4/4] iommu/vt-d: Remove hard coding PGSNP bit in PASID
entries
> From: Lu Baolu <baolu.lu@...ux.intel.com>
> Sent: Thursday, May 5, 2022 9:07 AM
>
> As enforce_cache_coherency has been introduced into the
> iommu_domain_ops,
> the kernel component which owns the iommu domain is able to opt-in its
> requirement for force snooping support. The iommu driver has no need to
> hard code the page snoop control bit in the PASID table entries anymore.
>
> Signed-off-by: Lu Baolu <baolu.lu@...ux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@...el.com>, with one nit:
> ---
> drivers/iommu/intel/pasid.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
> index 41a0e3b02c79..0abfa7fc7fb0 100644
> --- a/drivers/iommu/intel/pasid.c
> +++ b/drivers/iommu/intel/pasid.c
> @@ -710,9 +710,6 @@ int intel_pasid_setup_second_level(struct
> intel_iommu *iommu,
> pasid_set_fault_enable(pte);
> pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
Probably in a separate patch but above should really be renamed
to pasid_set_page_walk_snoop().
>
> - if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
> - pasid_set_pgsnp(pte);
> -
> /*
> * Since it is a second level only translation setup, we should
> * set SRE bit as well (addresses are expected to be GPAs).
> --
> 2.25.1
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