| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 5 May 2022 14:47:10 +0530
From: "Sajida Bhanu (Temp)" <quic_c_sbhanu@...cinc.com>
To: Ulf Hansson <ulf.hansson@...aro.org>
CC: <agross@...nel.org>, <bjorn.andersson@...aro.org>,
<adrian.hunter@...el.com>, <p.zabel@...gutronix.de>,
<chris@...ntf.net>, <venkatg@...eaurora.org>, <gdjakov@...sol.com>,
<quic_asutoshd@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-mmc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_rampraka@...cinc.com>, <quic_pragalla@...cinc.com>,
<quic_sartgarg@...cinc.com>, <quic_nitirawa@...cinc.com>,
<quic_sayalil@...cinc.com>
Subject: Re: [PATCH V5] mmc: sdhci-msm: Reset GCC_SDCC_BCR register for SDHC
On 5/4/2022 4:07 PM, Ulf Hansson wrote:
> On Wed, 27 Apr 2022 at 16:42, Ulf Hansson <ulf.hansson@...aro.org> wrote:
>> On Sun, 24 Apr 2022 at 18:02, Shaik Sajida Bhanu
>> <quic_c_sbhanu@...cinc.com> wrote:
>>> Reset GCC_SDCC_BCR register before every fresh initilazation. This will
>>> reset whole SDHC-msm controller, clears the previous power control
>>> states and avoids, software reset timeout issues as below.
>>>
>>> [ 5.458061][ T262] mmc1: Reset 0x1 never completed.
>>> [ 5.462454][ T262] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
>>> [ 5.469065][ T262] mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00007202
>>> [ 5.475688][ T262] mmc1: sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000
>>> [ 5.482315][ T262] mmc1: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000
>>> [ 5.488927][ T262] mmc1: sdhci: Present: 0x01f800f0 | Host ctl: 0x00000000
>>> [ 5.495539][ T262] mmc1: sdhci: Power: 0x00000000 | Blk gap: 0x00000000
>>> [ 5.502162][ T262] mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x00000003
>>> [ 5.508768][ T262] mmc1: sdhci: Timeout: 0x00000000 | Int stat: 0x00000000
>>> [ 5.515381][ T262] mmc1: sdhci: Int enab: 0x00000000 | Sig enab: 0x00000000
>>> [ 5.521996][ T262] mmc1: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
>>> [ 5.528607][ T262] mmc1: sdhci: Caps: 0x362dc8b2 | Caps_1: 0x0000808f
>>> [ 5.535227][ T262] mmc1: sdhci: Cmd: 0x00000000 | Max curr: 0x00000000
>>> [ 5.541841][ T262] mmc1: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000
>>> [ 5.548454][ T262] mmc1: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000
>>> [ 5.555079][ T262] mmc1: sdhci: Host ctl2: 0x00000000
>>> [ 5.559651][ T262] mmc1: sdhci_msm: ----------- VENDOR REGISTER DUMP-----------
>>> [ 5.566621][ T262] mmc1: sdhci_msm: DLL sts: 0x00000000 | DLL cfg: 0x6000642c | DLL cfg2: 0x0020a000
>>> [ 5.575465][ T262] mmc1: sdhci_msm: DLL cfg3: 0x00000000 | DLL usr ctl: 0x00010800 | DDR cfg: 0x80040873
>>> [ 5.584658][ T262] mmc1: sdhci_msm: Vndr func: 0x00018a9c | Vndr func2 : 0xf88218a8 Vndr func3: 0x02626040
>>>
>>> Fixes: 0eb0d9f4de34 ("mmc: sdhci-msm: Initial support for Qualcomm chipsets")
>>> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>
>> So this looks good to me, but I can't apply it until I get a patch
>> that updates the DT doc too.
> Okay, so since we are (I have already queued the patches for v5.19)
> moving the DT bindings into the yaml format, I decided to queue
> $subject patch, as is, for fixes. Moreover, I added a stable tag to
> it.
>
> Please send and patch on top of the new yaml based DT bindings to add
> the property for the reset.
>
> Thanks and kind regards
> Uffe
>
>
>> Kind regards
>> Uffe
Hi,
Sure Thank you.
Sure will post the YAML based DT bindings for resets changes once base
YAML changes merged.
Thanks,
Sajida
>>
>>> ---
>>>
>>> Changes since V4:
>>> - Called reset_control_put() in error path.
>>>
>>> Changes since V3:
>>> - Used reset controller local variable as suggested by
>>> Bjorn Andersson.
>>> - Passed NULL as a parameter to
>>> devm_reset_control_get_optional_exclusive() as suggested by
>>> Bjorn Andersson.
>>> - Replaced devm_reset_control_get_optional_exclusive() with
>>> reset_control_get_optional_exclusive() and called
>>> reset_control_put() before returning to clear the reset
>>> controller as suggested by Bjorn Andersson.
>>>
>>> Changes since V2:
>>> - Dropped new line after fixes tag as suggested by Bjorn
>>> Andersson.
>>> - Passed device structure instead of passing platform_device
>>> structure as a argument for sdhci_msm_gcc_reset() as suggested
>>> by Bjorn Andersson.
>>> - Replaced dev_err() with dev_err_probe() as suggested by Bjorn
>>> Andersson.
>>>
>>> Changes since V1:
>>> - Added fixes tag as suggested by Ulf Hansson.
>>> - Replaced devm_reset_control_get() with
>>> devm_reset_control_get_optional_exclusive() as suggested by
>>> Ulf Hansson.
>>> ---
>>> drivers/mmc/host/sdhci-msm.c | 42 ++++++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 42 insertions(+)
>>>
>>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
>>> index 50c71e0..ff9f5b6 100644
>>> --- a/drivers/mmc/host/sdhci-msm.c
>>> +++ b/drivers/mmc/host/sdhci-msm.c
>>> @@ -17,6 +17,7 @@
>>> #include <linux/regulator/consumer.h>
>>> #include <linux/interconnect.h>
>>> #include <linux/pinctrl/consumer.h>
>>> +#include <linux/reset.h>
>>>
>>> #include "sdhci-pltfm.h"
>>> #include "cqhci.h"
>>> @@ -2482,6 +2483,43 @@ static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
>>> of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
>>> }
>>>
>>> +static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)
>>> +{
>>> + struct reset_control *reset;
>>> + int ret = 0;
>>> +
>>> + reset = reset_control_get_optional_exclusive(dev, NULL);
>>> + if (IS_ERR(reset))
>>> + return dev_err_probe(dev, PTR_ERR(reset),
>>> + "unable to acquire core_reset\n");
>>> +
>>> + if (!reset)
>>> + return ret;
>>> +
>>> + ret = reset_control_assert(reset);
>>> + if (ret) {
>>> + reset_control_put(reset);
>>> + return dev_err_probe(dev, ret, "core_reset assert failed\n");
>>> + }
>>> +
>>> + /*
>>> + * The hardware requirement for delay between assert/deassert
>>> + * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
>>> + * ~125us (4/32768). To be on the safe side add 200us delay.
>>> + */
>>> + usleep_range(200, 210);
>>> +
>>> + ret = reset_control_deassert(reset);
>>> + if (ret) {
>>> + reset_control_put(reset);
>>> + return dev_err_probe(dev, ret, "core_reset deassert failed\n");
>>> + }
>>> +
>>> + usleep_range(200, 210);
>>> + reset_control_put(reset);
>>> +
>>> + return ret;
>>> +}
>>>
>>> static int sdhci_msm_probe(struct platform_device *pdev)
>>> {
>>> @@ -2529,6 +2567,10 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>>>
>>> msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
>>>
>>> + ret = sdhci_msm_gcc_reset(&pdev->dev, host);
>>> + if (ret)
>>> + goto pltfm_free;
>>> +
>>> /* Setup SDCC bus voter clock. */
>>> msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
>>> if (!IS_ERR(msm_host->bus_clk)) {
>>> --
>>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>>> of Code Aurora Forum, hosted by The Linux Foundation
>>>
Powered by blists - more mailing lists