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Date: Thu, 5 May 2022 13:38:02 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH 6/6] arm64: dts: qcom: sdm630: correct QFPROM byte offsets
The NVMEM bindings expect that 'bits' property holds offset and size of
region within a byte, so it applies a constraint of <0, 7> for the
offset. Using 25 as HSTX trim offset is within 4-byte QFPROM word, but
outside of the byte:
sdm630-sony-xperia-nile-discovery.dtb: qfprom@...000: hstx-trim@240:bits:0:0: 25 is greater than the maximum of 7
sdm630-sony-xperia-nile-discovery.dtb: qfprom@...000: gpu-speed-bin@...0:bits:0:0: 21 is greater than the maximum of 7
Align the offsets to match the bindings.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
Not tested on SDM630 hardware, but similar behavior on SDM845 works
fine (although causes a read of 4 bytes instead of 1).
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 505e10674cb6..c713aa6e7044 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -558,13 +558,13 @@ qfprom: qfprom@...000 {
#size-cells = <1>;
qusb2_hstx_trim: hstx-trim@240 {
- reg = <0x240 0x1>;
- bits = <25 3>;
+ reg = <0x243 0x1>;
+ bits = <1 3>;
};
gpu_speed_bin: gpu-speed-bin@...0 {
- reg = <0x41a0 0x1>;
- bits = <21 7>;
+ reg = <0x41a2 0x1>;
+ bits = <5 7>;
};
};
--
2.32.0
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