Message-ID: <ce4e4fe6-fe20-22de-2443-d0d199a973c4@huawei.com>
Date:   Fri, 6 May 2022 14:25:29 +0800
From:   "liuqi (BA)" <liuqi115@...wei.com>
To:     Suzuki K Poulose <suzuki.poulose@....com>,
        <mathieu.poirier@...aro.org>
CC:     <coresight@...ts.linaro.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <linuxarm@...wei.com>,
        <Jonathan_Lucas@...tor.com>
Subject: Re: [PATCH v5 2/2] Documentation: Add document for UltraSoc SMB
 drivers


Hi Suzuki,

thanks for your review, some replies inline.

On 2022/5/6 0:22, Suzuki K Poulose wrote:
> On 16/04/2022 09:39, Qi Liu wrote:
>> This patch bring in a documentation for UltraSoc SMB drivers.
>> It simple descripts the device, sysfs interface and the
>> firmware bindings.
>>
>> Signed-off-by: Qi Liu <liuqi115@...wei.com>
>> ---
>>   .../trace/coresight/ultrasoc-smb.rst          | 79 +++++++++++++++++++
>>   1 file changed, 79 insertions(+)
>>   create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst
>>
>> diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst 
>> b/Documentation/trace/coresight/ultrasoc-smb.rst
>> new file mode 100644
>> index 000000000000..024fa4492f42
>> --- /dev/null
>> +++ b/Documentation/trace/coresight/ultrasoc-smb.rst
>> @@ -0,0 +1,79 @@
>> +.. SPDX-License-Identifier: GPL-2.0
>> +
>> +======================================
>> +UltraSoc - HW Assisted Tracing on SoC
>> +======================================
>> +   :Author:   Qi Liu <liuqi115@...wei.com>
>> +   :Date:     March 2022
>> +
>> +Introduction
>> +------------
>> +
>> +UltraSoc SMB is a per SCCL hardware, and it provides a way to buffer 
>> and store
> 
> nit: what is SCCL ?

SCCL is super CPU cluster, I'll add the full name next time.

> 
>> +CPU trace messages in a region of shared system memory. SMB is 
>> plugged as
>> +a coresight sink device and the corresponding trace generators (ETM) are
>> +plugged in as source devices.
>> +
>> +Sysfs files and directories
>> +---------------------------
>> +
>> +The SMB devices appear on the existing coresight bus alongside the other
>> +coresight devices::
>> +
>> +    $# ls /sys/bus/coresight/devices/
>> +    ultra_smb0   ultra_smb1   ultra_smb2   ultra_smb3
>> +
>> +The ``ultra_smb<N>`` named SMB associated with SCCL.::
>> +
>> +    $# ls /sys/bus/coresight/devices/ultra_smb0
>> +    enable_sink   mgmt
>> +    $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt
>> +    buf_size  buf_status  read_pos  write_pos
>> +
>> +*Key file items are:-*
>> +   * ``read_pos``: Shows the value held by UltraSoc SMB Read Pointer 
>> register.
>> +   * ``write_pos``: Shows the value held by UltraSoc SMB Write 
>> Pointer register.
>> +   * ``buf_status``: Shows the value held by UltraSoc SMB status 
>> register.
>> +             BIT(0) is zero means buffer is empty.
>> +   * ``buf_size``: Shows the buffer size of each UltraSoc SMB device.
>> +
>> +Firmware Bindings
>> +---------------------------
>> +
>> +Firmware binding of SMB device describes SMB device indentifier, 
>> resource
>> +information and graph structure.
>> +
>> +SMB is platform device and device id is "HISI03A1", resource of 
>> device is
>> +declared using the _CRS method. Each SMB must present two base address,
>> +the first one is the configuration base address of SMB device, the 
>> second
>> +one is the base address of shared system memory.
>> +
>> +examples::
>> +
>> +    Device(USMB) {                                               \
>> +      Name(_HID, "HISI03A1")                                     \
>> +      Name(_CRS, ResourceTemplate() {                            \
>> +          MEM_RESRC(0x95100000, 0x951FFFFF, 0x100000)            \
>> +          MEM_RESRC(0x50000000, 0x53FFFFFF, 0x4000000)           \
>> +      })                                                         \
> 
> 
>> +      Name(_DSD, Package() {                                     \
>> +        ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"),          \
> 
> nit: May be add a comment here to explain, use Arm CoreSight Graph
> ACPI bindings to describe the connections.

got it, will add a comment above, thanks.
> 
>> +        Package() {                                              \
>> +          0,                                                     \
>> +          1,                                                     \
>> +          Package() {                                            \
>> +            1,                                                   \
>> +            ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"),      \
>> +            8,                                                   \
>> +            Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0},       \
>> +            Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0},       \
>> +            Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0},       \
>> +            Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0},       \
>> +            Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0},       \
>> +            Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0},       \
>> +            Package() {0xe, 0, \_SB.S00.SL11.CL2E.F014, 0},       \
>> +            Package() {0xf, 0, \_SB.S00.SL11.CL2F.F015, 0},       \
>> +          }                                                      \
> 
> Interesting, are there multiple input ports for the SMB ? We haven't
> seen an instance of a "sink" that supports this. So, would be
> interesting to see how the driver copes with that scenario.
> 
> Suzuki
> 
> yes, as there are 8 clusters in a SCCL, and each cluster use one funnel 
device to transmit core trace data, so SMB has 8 input funnel ports.

Thanks,
Qi
> 
>> +        }                                                        \
>> +      })                                                         \
>> +    }
> 
> .

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