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Message-ID: <67391ba6-c7c4-d164-1a12-cd35f942d9a0@linux.intel.com>
Date: Fri, 6 May 2022 10:39:24 -0400
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: Yang Weijiang <weijiang.yang@...el.com>, pbonzini@...hat.com,
jmattson@...gle.com, seanjc@...gle.com, like.xu.linux@...il.com,
vkuznets@...hat.com, wei.w.wang@...el.com, kvm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v11 06/16] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for
guest Arch LBR
On 5/5/2022 11:32 PM, Yang Weijiang wrote:
> From: Like Xu <like.xu@...ux.intel.com>
>
> The number of Arch LBR entries available is determined by the value
> in host MSR_ARCH_LBR_DEPTH.DEPTH. The supported LBR depth values are
> enumerated in CPUID.(EAX=01CH, ECX=0):EAX[7:0]. For each bit "n" set
> in this field, the MSR_ARCH_LBR_DEPTH.DEPTH value of "8*(n+1)" is
> supported. In the first generation of Arch LBR, max entry size is 32,
> host configures the max size and guest always honors the setting.
>
> Write to MSR_ARCH_LBR_DEPTH has side-effect, all LBR entries are reset
> to 0. Kernel PMU driver can leverage this effect to do fask reset to
> LBR record MSRs. KVM allows guest to achieve it when Arch LBR records
> MSRs are passed through to the guest.
>
> Signed-off-by: Like Xu <like.xu@...ux.intel.com>
> Co-developed-by: Yang Weijiang <weijiang.yang@...el.com>
> Signed-off-by: Yang Weijiang <weijiang.yang@...el.com>
> ---
> arch/x86/include/asm/kvm_host.h | 3 ++
> arch/x86/kvm/vmx/pmu_intel.c | 50 ++++++++++++++++++++++++++++++++-
> 2 files changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 4ff36610af6a..753e3ecac1a1 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -534,6 +534,9 @@ struct kvm_pmu {
> * redundant check before cleanup if guest don't use vPMU at all.
> */
> u8 event_count;
> +
> + /* Guest arch lbr depth supported by KVM. */
> + u64 kvm_arch_lbr_depth;
> };
>
> struct kvm_pmu_ops;
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index b82b6709d7a8..e2b5fc1f4f1a 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -192,6 +192,12 @@ static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index)
> if (!intel_pmu_lbr_is_enabled(vcpu))
> return ret;
>
> + if (index == MSR_ARCH_LBR_DEPTH) {
> + if (kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR))
> + ret = guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR);
> + return ret;
> + }
> +
> ret = (index == MSR_LBR_SELECT) || (index == MSR_LBR_TOS) ||
> (index >= records->from && index < records->from + records->nr) ||
> (index >= records->to && index < records->to + records->nr);
> @@ -205,7 +211,7 @@ static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index)
> static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
> {
> struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
> - int ret;
> + int ret = 0;
>
I don't think you need this change anymore, since the MSR_ARCH_LBR_DEPTH
has been moved to the other place.
After the above is removed, the patch looks good to me.
Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
Thanks,
Kan
> switch (msr) {
> case MSR_CORE_PERF_FIXED_CTR_CTRL:
> @@ -342,10 +348,26 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
> return true;
> }
>
> +/*
> + * Check if the requested depth value the same as that of host.
> + * When guest/host depth are different, the handling would be tricky,
> + * so now only max depth is supported for both host and guest.
> + */
> +static bool arch_lbr_depth_is_valid(struct kvm_vcpu *vcpu, u64 depth)
> +{
> + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
> +
> + if (!kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR))
> + return false;
> +
> + return (depth == pmu->kvm_arch_lbr_depth);
> +}
> +
> static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> {
> struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
> struct kvm_pmc *pmc;
> + struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
> u32 msr = msr_info->index;
>
> switch (msr) {
> @@ -361,6 +383,9 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
> msr_info->data = 0;
> return 0;
> + case MSR_ARCH_LBR_DEPTH:
> + msr_info->data = lbr_desc->records.nr;
> + return 0;
> default:
> if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
> (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
> @@ -387,6 +412,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> {
> struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
> struct kvm_pmc *pmc;
> + struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
> u32 msr = msr_info->index;
> u64 data = msr_info->data;
> u64 reserved_bits;
> @@ -421,6 +447,16 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> return 0;
> }
> break;
> + case MSR_ARCH_LBR_DEPTH:
> + if (!arch_lbr_depth_is_valid(vcpu, data))
> + return 1;
> + lbr_desc->records.nr = data;
> + /*
> + * Writing depth MSR from guest could either setting the
> + * MSR or resetting the LBR records with the side-effect.
> + */
> + wrmsrl(MSR_ARCH_LBR_DEPTH, lbr_desc->records.nr);
> + return 0;
> default:
> if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
> (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
> @@ -555,6 +591,18 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
>
> if (lbr_desc->records.nr)
> bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1);
> +
> + if (!kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR))
> + return;
> +
> + entry = kvm_find_cpuid_entry(vcpu, 28, 0);
> + if (entry) {
> + /*
> + * The depth mask in CPUID is fixed to host supported
> + * value when userspace sets guest CPUID.
> + */
> + pmu->kvm_arch_lbr_depth = fls(entry->eax & 0xff) * 8;
> + }
> }
>
> static void intel_pmu_init(struct kvm_vcpu *vcpu)
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