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Message-Id: <20220508185957.3629088-29-clabbe@baylibre.com>
Date: Sun, 8 May 2022 18:59:52 +0000
From: Corentin Labbe <clabbe@...libre.com>
To: heiko@...ech.de, ardb@...nel.org, herbert@...dor.apana.org.au,
krzysztof.kozlowski+dt@...aro.org, robh+dt@...nel.org
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-crypto@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-rockchip@...ts.infradead.org,
Corentin Labbe <clabbe@...libre.com>
Subject: [PATCH v7 28/33] arm64: dts: rockchip: rk3399: add crypto node
The rk3399 has a crypto IP handled by the rk3288 crypto driver so adds a
node for it.
Signed-off-by: Corentin Labbe <clabbe@...libre.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 8db8b2dba12d..27ab2c377140 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -582,6 +582,26 @@ saradc: saradc@...00000 {
status = "disabled";
};
+ crypto0: crypto@...b0000 {
+ compatible = "rockchip,rk3399-crypto";
+ reg = <0x0 0xff8b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
+ clock-names = "hclk_master", "hclk_slave", "sclk";
+ resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
+ reset-names = "rst_master", "rst_slave", "crypto-rst";
+ };
+
+ crypto1: crypto@...b8000 {
+ compatible = "rockchip,rk3399-crypto";
+ reg = <0x0 0xff8b8000 0x0 0x4000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
+ clock-names = "hclk_master", "hclk_slave", "sclk";
+ resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
+ reset-names = "rst_master", "rst_slave", "crypto-rst";
+ };
+
i2c1: i2c@...10000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff110000 0x0 0x1000>;
--
2.35.1
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