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Message-ID: <YnlpU+sCfO86+qc2@google.com>
Date: Mon, 9 May 2022 12:19:47 -0700
From: Matthias Kaehlcke <mka@...omium.org>
To: Rob Herring <robh@...nel.org>
Cc: Sibi Sankar <quic_sibis@...cinc.com>, swboyd@...omium.org,
linux-remoteproc@...r.kernel.org, devicetree@...r.kernel.org,
bjorn.andersson@...aro.org, robh+dt@...nel.org,
mathieu.poirier@...aro.org, krzysztof.kozlowski@...onical.com,
agross@...nel.org, dianders@...omium.org, ohad@...ery.com,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
evgreen@...omium.org
Subject: Re: [PATCH v2 1/2] dt-bindings: remoteproc: qcom: Add SC7280 MSS
bindings
On Mon, May 09, 2022 at 07:20:58AM -0500, Rob Herring wrote:
> On Mon, 09 May 2022 13:23:17 +0530, Sibi Sankar wrote:
> > Add MSS PIL loading bindings for SC7280 SoCs.
> >
> > Signed-off-by: Sibi Sankar <quic_sibis@...cinc.com>
> > ---
> > .../bindings/remoteproc/qcom,sc7280-mss-pil.yaml | 261 +++++++++++++++++++++
> > 1 file changed, 261 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml
> >
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/
The culprit is this snippet in arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi:
/* Modem setup is different on Chrome setups than typical Qualcomm setup */
&remoteproc_mpss {
status = "okay";
compatible = "qcom,sc7280-mss-pil";
iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
memory-region = <&mba_mem>, <&mpss_mem>;
};
The original compatible string from sc7280.dtsi is 'qcom,sc7280-mpss-pas'.
> remoteproc@...0000: clock-names:1: 'snoc_axi' was expected
> arch/arm64/boot/dts/qcom/sc7280-crd.dtb
> arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dtb
> arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dtb
> arch/arm64/boot/dts/qcom/sc7280-idp2.dtb
> arch/arm64/boot/dts/qcom/sc7280-idp.dtb
>
> remoteproc@...0000: clock-names:2: 'offline' was expected
> arch/arm64/boot/dts/qcom/sc7280-crd.dtb
> arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dtb
> arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dtb
> arch/arm64/boot/dts/qcom/sc7280-idp2.dtb
> arch/arm64/boot/dts/qcom/sc7280-idp.dtb
The fix probably consists in adding overrides for 'clocks' and
'clock-names' to the extension in sc7280-chrome-common.dtsi, unless
we add a dedicated 'qcom,sc7280-mss-pil' node to sc7280.dtsi. This
can be done once the binding landed.
> remoteproc@...0000: 'interconnects' is a required property
> arch/arm64/boot/dts/qcom/sc7280-crd.dtb
> arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dtb
> arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dtb
> arch/arm64/boot/dts/qcom/sc7280-idp2.dtb
> arch/arm64/boot/dts/qcom/sc7280-idp.dtb
This can be fixed by adding an 'interconnects' to either the
extension in sc7280-chrome-common.dtsi, or the original node if
'qcom,sc7280-mpss-pas' uses the same interconnect.
> remoteproc@...0000: reset-names:1: 'pdc_sync' was expected
> arch/arm64/boot/dts/qcom/sc7280-crd.dtb
> arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dtb
> arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dtb
> arch/arm64/boot/dts/qcom/sc7280-idp2.dtb
> arch/arm64/boot/dts/qcom/sc7280-idp.dtb
>
This could be fixed by aligning the reset names of the
'qcom,sc7280-mpss-pas' and 'qcom,sc7280-mss-pil' bindings.
The reset is called 'pdc_reset' for 'mpss-pas', and 'pdc_sync'
for 'mpss-pil'.
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