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Message-ID: <743c06e8-a53b-4546-cad7-27e7a3ef77b6@microchip.com>
Date: Mon, 9 May 2022 06:26:47 +0000
From: <Claudiu.Beznea@...rochip.com>
To: <michael@...le.cc>, <Kavyasree.Kotagiri@...rochip.com>,
<Nicolas.Ferre@...rochip.com>
CC: <arnd@...db.de>, <olof@...om.net>, <soc@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski@...onical.com>,
<alexandre.belloni@...tlin.com>, <Tudor.Ambarus@...rochip.com>,
<Horatiu.Vultur@...rochip.com>
Subject: Re: [PATCH v4 11/13] ARM: dts: lan966x: add serdes node
On 03.05.2022 01:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add the SerDes node. On the LAN966x SoC these SerDes are used to connect
> network PHYs.
>
> By default, that node is disabled.
>
> Signed-off-by: Michael Walle <michael@...le.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 7020b31322d8..d8185f5c7bfc 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -500,6 +500,14 @@ hwmon: hwmon@...10180 {
> clocks = <&sys_clk>;
> };
>
> + serdes: serdes@...2c000 {
> + compatible = "microchip,lan966x-serdes";
> + reg = <0xe202c000 0x9c>,
> + <0xe2004010 0x4>;
> + #phy-cells = <2>;
> + status = "disabled";
> + };
> +
> gic: interrupt-controller@...11000 {
> compatible = "arm,gic-400", "arm,cortex-a7-gic";
> #interrupt-cells = <3>;
> --
> 2.30.2
>
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