lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <c313e9c9-97eb-8273-5bb7-553692e8e2f5@gmail.com>
Date:   Mon, 9 May 2022 15:05:33 +0800
From:   Like Xu <like.xu.linux@...il.com>
To:     Sandipan Das <sandipan.das@....com>
Cc:     peterz@...radead.org, bp@...en8.de, dave.hansen@...ux.intel.com,
        acme@...nel.org, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, namhyung@...nel.org,
        jolsa@...nel.org, tglx@...utronix.de, mingo@...hat.com,
        pbonzini@...hat.com, jmattson@...gle.com, eranian@...gle.com,
        puwen@...on.cn, ananth.narayan@....com, ravi.bangoria@....com,
        santosh.shukla@....com,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-perf-users@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH v4 5/7] perf/x86/amd/core: Add PerfMonV2 counter control

On 27/4/2022 7:31 pm, Sandipan Das wrote:

>   static void amd_pmu_add_event(struct perf_event *event)
>   {
>   	if (needs_branch_stack(event))
> @@ -1216,6 +1251,11 @@ static int __init amd_core_pmu_init(void)
>   		x86_pmu.num_counters = ebx.split.num_core_pmc;
>   
>   		amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1;
> +
> +		/* Update PMC handling functions */
> +		x86_pmu.enable_all = amd_pmu_v2_enable_all;
> +		x86_pmu.disable_all = amd_pmu_v2_disable_all;
> +		x86_pmu.enable = amd_pmu_v2_enable_event;
>   	}

Considering the below part of code also run on the PerfMonV2 host

whatever the guest PMU version, how about updating these two use cases as well 
in this patch ?

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 262e39a85031..2f7c62e46314 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -1469,8 +1469,8 @@ void amd_pmu_enable_virt(void)
         cpuc->perf_ctr_virt_mask = 0;

         /* Reload all events */
-       amd_pmu_disable_all();
-       x86_pmu_enable_all(0);
+       amd_pmu.disable_all();
+       amd_pmu.enable_all(0);
  }
  EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);

@@ -1487,7 +1487,7 @@ void amd_pmu_disable_virt(void)
         cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;

         /* Reload all events */
-       amd_pmu_disable_all();
-       x86_pmu_enable_all(0);
+       amd_pmu.disable_all();
+       amd_pmu.enable_all(0);
  }
  EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ