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Message-ID: <CAE-0n51VpM-sw+1MLqtx+-YSa9ayQX+=tgZ7zLfnMEa5+742oQ@mail.gmail.com>
Date: Tue, 10 May 2022 10:45:15 -0700
From: Stephen Boyd <swboyd@...omium.org>
To: "Joseph S. Barrera III" <joebar@...omium.org>,
LKML <linux-kernel@...r.kernel.org>
Cc: Douglas Anderson <dianders@...omium.org>,
Alexandru M Stan <amstan@...omium.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v4 2/5] arm64: dts: qcom: sc7180: Add mrbland dts files
Quoting Joseph S. Barrera III (2022-05-05 10:41:13)
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
> new file mode 100644
> index 000000000000..e1c1ea09b690
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
> @@ -0,0 +1,352 @@
[...]
> +
> +&ap_tp_i2c {
> + status = "disabled";
> +};
> +
> +&backlight {
> + pwms = <&cros_ec_pwm 0>;
> +};
> +
> +&camcc {
> + status = "okay";
> +};
> +
> +&dsi0 {
> +
> + panel: panel@0 {
Can we have a note here like in the bridge chip dtsi files that says the
compatible is filled in per board?
/* Compatible will be filled in per-board */
> + reg = <0>;
> + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&vdd_reset_1800>;
> + avdd-supply = <&avdd_lcd>;
> + avee-supply = <&avee_lcd>;
> + pp1800-supply = <&v1p8_mipi>;
> + pp3300-supply = <&pp3300_dx_edp>;
> + backlight = <&backlight>;
> + rotation = <270>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + panel_in: endpoint {
> + remote-endpoint = <&dsi0_out>;
> + };
> + };
> + };
> + };
> +
[...]
> +
> +/* PINCTRL - board-specific pinctrl */
> +
> +&tlmm {
> + gpio-line-names = "HUB_RST_L",
> + "AP_RAM_ID0",
[..]
> + avee_lcd_en: avee-lcd_en {
Same underscore comment as patch #1
> + pinmux {
> + pins = "gpio21";
> + function = "gpio";
> + };
> +
> + pinconf {
> + pins = "gpio21";
> + drive-strength = <2>;
> + bias-disable;
> + };
> + };
> +
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