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Message-ID: <CAK8P3a1k8y8U99bBmqBYE1vYAc0q-UeaM0oLP4tTHZCpyYNOgA@mail.gmail.com>
Date:   Tue, 10 May 2022 09:07:59 +0200
From:   Arnd Bergmann <arnd@...db.de>
To:     Jacky Huang <ychuang3@...oton.com>
Cc:     Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        DTML <devicetree@...r.kernel.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        ychuang570808@...il.com, Rob Herring <robh+dt@...nel.org>,
        Stephen Boyd <sboyd@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>, SoC Team <soc@...nel.org>,
        cfli0@...oton.com
Subject: Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC

On Tue, May 10, 2022 at 5:25 AM Jacky Huang <ychuang3@...oton.com> wrote:
>
> This patch series adds initial support for Nuvoton MA35D1 SoC,
> include initial dts and clock controller binding.
>

This looks fine in principle, but we are getting close to the merge window and
should finalize this quickly to make it into v5.19. I see that you don't have a
console device, as commented in the .dts patch. Normally I prefer merging
platforms only when there is at least rudimentary support for booting into
an initramfs with a serial console, but this is a flexible rule.

As with the changelog text for the .dts file, please explain in the [PATCH 0/5]
cover letter what the status is.

Regarding continued maintainership, we should discuss how you plan to
maintain this platform. In particular, there should be an entry in the
MAINTAINERS
file for the platform, either pointing to yourself, or adding it to the  NPCM or
WPCM450 entries if this chip is in the same family. Is this also a BMC
implementation, or is it something different?

       Arnd

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