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Message-ID: <20220511144958.GA286838-robh@kernel.org>
Date: Wed, 11 May 2022 09:49:58 -0500
From: Rob Herring <robh@...nel.org>
To: Sumit Gupta <sumitg@...dia.com>
Cc: linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, thierry.reding@...il.com,
jonathanh@...dia.com, kbuild-all@...ts.01.org, bbasu@...dia.com,
vsethi@...dia.com, jsequeira@...dia.com
Subject: Re: [Patch v5 6/9] dt-bindings: arm: tegra: Add NVIDIA Tegra234
CBB2.0 binding
On Fri, May 06, 2022 at 04:42:14PM +0530, Sumit Gupta wrote:
> Add device-tree binding documentation to represent CBB2.0 (Control
> Backbone) error handling driver. The driver prints debug information
> about failed transaction on receiving interrupt from CBB2.0.
Same issues in this one that I won't repeat...
>
> Signed-off-by: Sumit Gupta <sumitg@...dia.com>
> ---
> .../arm/tegra/nvidia,tegra234-cbb.yaml | 70 +++++++++++++++++++
> 1 file changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml
> new file mode 100644
> index 000000000000..fa4383be19d8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: NVIDIA Tegra CBB 2.0 Error handling driver device tree bindings
> +
> +maintainers:
> + - Sumit Gupta <sumitg@...dia.com>
> +
> +description: |+
> + The Control Backbone (CBB) is comprised of the physical path from an initiator to a target's
> + register configuration space. CBB 2.0 consists of multiple sub-blocks connected to each other
> + to create a topology. The Tegra234 SoC has different fabrics based on CBB2.0 architecture which
> + include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and "CBB central fabric".
> +
> + In CBB 2.0, each initiator which can issue transactions connects to a Root Master Node (MN)
> + before it connects to any other element of the fabric. Each Root MN contains a Error Monitor
> + (EM) which detects and logs error. Interrupts from various EM blocks are collated by Error
> + Notifier (EN) which is per fabric and presents a single interrupt from fabric to the SoC
> + interrupt controller.
> +
> + The driver handles errors from CBB due to illegal register accesses and prints debug information
> + about failed transaction on receiving the interrupt from EN. Debug information includes Error
> + Code, Error Description, MasterID, Fabric, SlaveID, Address, Cache, Protection, Security Group
> + etc on receiving error notification.
> +
> + If the Error Response Disable (ERD) is set/enabled for an initiator, then SError or Data abort
> + exception error response is masked and an interrupt is used for reporting errors due to illegal
> + accesses from that initiator. The value returned on read failures is '0xFFFFFFFF' for
> + compatibility with PCIE.
> +
> +properties:
> + $nodename:
> + pattern: "^[a-z]+-fabric@[0-9a-f]+$"
> +
> + compatible:
> + enum:
> + - nvidia,tegra234-aon-fabric
> + - nvidia,tegra234-bpmp-fabric
> + - nvidia,tegra234-cbb-fabric
> + - nvidia,tegra234-dce-fabric
> + - nvidia,tegra234-rce-fabric
> + - nvidia,tegra234-sce-fabric
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: secure interrupt from error notifier
> +
> +additionalProperties: true
True is only allowed for common bindings included in other bindings.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + cbb-fabric@...0000 {
> + compatible = "nvidia,tegra234-cbb-fabric";
> + reg = <0x13a00000 0x400000>;
> + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
> + };
> --
> 2.17.1
>
>
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