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Message-ID: <20f078a8-f050-127f-b720-b5fc8c893c9c@collabora.com>
Date:   Wed, 11 May 2022 17:04:48 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     xinlei.lee@...iatek.com, chunkuang.hu@...nel.org,
        p.zabel@...gutronix.de, airlied@...ux.ie, daniel@...ll.ch,
        matthias.bgg@...il.com
Cc:     dri-devel@...ts.freedesktop.org,
        linux-mediatek@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        rex-bc.chen@...iatek.com, jitao.shi@...iatek.com
Subject: Re: [PATCH v5, 4/5] drm/mediatek: keep dsi as LP00 before dcs cmds
 transfer

Il 11/05/22 04:36, xinlei.lee@...iatek.com ha scritto:
> From: Jitao Shi <jitao.shi@...iatek.com>
> 
> To comply with the panel sequence, hold the mipi signal to LP00 before the dcs cmds transmission,
> and pull the mipi signal high from LP00 to LP11 until the start of the dcs cmds transmission.
> The normal panel timing is :
> (1) pp1800 DC pull up
> (2) avdd & avee AC pull high
> (3) lcm_reset pull high -> pull low -> pull high
> (4) Pull MIPI signal high (LP11) -> initial code -> send video data(HS mode)
> The power-off sequence is reversed.
> If dsi is not in cmd mode, then dsi will pull the mipi signal high in the mtk_output_dsi_enable function.
> The delay in lane_ready func is the reaction time of dsi_rx after pulling up the mipi signal.
> 
> Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge API")
> 
> Signed-off-by: Jitao Shi <jitao.shi@...iatek.com>
> Signed-off-by: Xinlei Lee <xinlei.lee@...iatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>

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