linux-kernel - Re: [PATCH v2] PCI: cadence: Clear FLR in device capabilities register

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Date:   Wed, 11 May 2022 17:02:35 +0100
From:   Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To:     Parshuram Raju Thombare <pthombar@...ence.com>,
        tjoseph@...ence.com, bhelgaas@...gle.com, robh@...nel.org,
        kishon@...com, kw@...ux.com
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>, mparab@...ence.com,
        linux-pci@...r.kernel.org, linux-omap@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] PCI: cadence: Clear FLR in device capabilities register

On Mon, 15 Nov 2021 23:39:16 -0800, Parshuram Raju Thombare wrote:
> From: Parshuram Thombare <pthombar@...ence.com>
> 
> Clear FLR (Function Level Reset) from device capabilities
> registers for all physical functions.
> 
> During FLR, the Margining Lane Status and Margining Lane Control
> registers should not be reset, as per PCIe specification.
> However, the controller incorrectly resets these registers upon FLR.
> This causes PCISIG compliance FLR test to fail. Hence preventing
> all functions from advertising FLR support if flag quirk_disable_flr
> is set.
> 
> [...]

Applied to pci/cadence, thanks!

[1/1] PCI: cadence: Clear FLR in device capabilities register
      https://git.kernel.org/lpieralisi/pci/c/d3dbd4d862

Thanks,
Lorenzo