linux-kernel - [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Message-Id: <20220511214038.2281398-1-heiko@sntech.de>
Date:   Wed, 11 May 2022 23:40:35 +0200
From:   Heiko Stuebner <heiko@...ech.de>
To:     palmer@...belt.com, paul.walmsley@...ive.com
Cc:     linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        wefu@...hat.com, guoren@...nel.org, atishp@...shpatra.org,
        anup@...infault.org, mick@....forth.gr, samuel@...lland.org,
        cmuellner@...ux.com, philipp.tomsich@...ll.eu, robh+dt@...nel.org,
        krzk+dt@...nel.org, devicetree@...r.kernel.org,
        Heiko Stuebner <heiko@...ech.de>
Subject: [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant

This series is based on the alternatives changes done in my svpbmt series
and thus also depends on Atish's isa-extension parsing series.

It implements using the cache-management instructions from the  Zicbom-
extension to handle cache flush, etc actions on platforms needing them.

SoCs using cpu cores from T-Head like the Allwinne D1 implement a
different set of cache instructions. But while they are different,
instructions they provide the same functionality, so a variant can
easly hook into the existing alternatives mechanism on those.


As Palmer suggested, merging might have to wait until the cache
instructions have landed in compilers, but I wanted to put the
block-size changes out there for people to look at already and
also update the series to match the current svpbmt state.


changes in v2:
- cbom-block-size is hardware-specific and comes from firmware
- update Kconfig name to use the ISA extension name
- select the ALTERNATIVES symbol when enabled
- shorten the line lengths of the errata-assembly

Heiko Stuebner (3):
  dt-bindings: riscv: document cbom-block-size
  riscv: Implement Zicbom-based cache management operations
  riscv: implement cache-management errata for T-Head SoCs

 .../devicetree/bindings/riscv/cpus.yaml       |  7 ++
 arch/riscv/Kconfig                            | 15 +++
 arch/riscv/Kconfig.erratas                    | 10 ++
 arch/riscv/errata/thead/errata.c              |  5 +
 arch/riscv/include/asm/cacheflush.h           |  6 ++
 arch/riscv/include/asm/errata_list.h          | 80 +++++++++++++++-
 arch/riscv/include/asm/hwcap.h                |  1 +
 arch/riscv/kernel/cpu.c                       |  1 +
 arch/riscv/kernel/cpufeature.c                | 17 ++++
 arch/riscv/kernel/setup.c                     |  2 +
 arch/riscv/mm/Makefile                        |  1 +
 arch/riscv/mm/dma-noncoherent.c               | 92 +++++++++++++++++++
 12 files changed, 235 insertions(+), 2 deletions(-)
 create mode 100644 arch/riscv/mm/dma-noncoherent.c

-- 
2.35.1