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Message-Id: <1652384021-46309-3-git-send-email-zhouyanjie@wanyeetech.com>
Date: Fri, 13 May 2022 03:33:40 +0800
From: 周琰杰 (Zhou Yanjie)
<zhouyanjie@...yeetech.com>
To: tsbogend@...ha.franken.de, paul@...pouillou.net,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-mips@...r.kernel.org, dongsheng.qiu@...enic.com,
aric.pzqi@...enic.com, rick.tyliu@...enic.com
Subject: [PATCH 2/3] MIPS: Ingenic: Refresh device tree for Ingenic SoCs and boards.
1.Add SSI nodes for X1000 SoC and X1830 SoC from Ingenic.
2.Refresh SSI related nodes in CU1000-Neo and CU1830-Neo.
3.The X1830 SoC used by the CU1830-Neo and the X1000 SoC
used by the CU1000-Neo are both single-core processors,
therefore the "OST_CLK_PERCPU_TIMER" ABI should not be
used in the OST nodes of the CU1830-Neo and CU1000-Neo,
it is just a coincidence that there is no problem now.
So replace the misused "OST_CLK_PERCPU_TIMER" ABI with
the correct "OST_CLK_EVENT_TIMER" ABI.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
---
arch/mips/boot/dts/ingenic/cu1000-neo.dts | 77 ++++++++++++++++---------------
arch/mips/boot/dts/ingenic/cu1830-neo.dts | 76 +++++++++++++++---------------
arch/mips/boot/dts/ingenic/x1000.dtsi | 20 ++++++++
arch/mips/boot/dts/ingenic/x1830.dtsi | 39 ++++++++++++++++
4 files changed, 138 insertions(+), 74 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
index 9c67b4f..b44d3b1 100644
--- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
+++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
@@ -31,42 +31,6 @@
};
};
- ssi: spi-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- num-chipselects = <1>;
-
- mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
- miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
- sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
-
- status = "okay";
-
- spi-max-frequency = <50000000>;
-
- sc16is752: expander@0 {
- compatible = "nxp,sc16is752";
- reg = <0>; /* CE0 */
- spi-max-frequency = <4000000>;
-
- clocks = <&exclk_sc16is752>;
-
- interrupt-parent = <&gpc>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- exclk_sc16is752: sc16is752 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
- };
- };
-
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";
@@ -90,7 +54,7 @@
&ost {
/* 1500 kHz for the system timer and clocksource */
- assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
+ assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};
@@ -101,6 +65,39 @@
pinctrl-0 = <&pins_uart2>;
};
+&ssi {
+ status = "okay";
+
+ num-cs = <2>;
+ cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_ssi>;
+
+ sc16is752: expander@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>; /* CE0 */
+
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ spi-max-frequency = <4000000>;
+
+ clocks = <&exclk_sc16is752>;
+
+ interrupt-parent = <&gpc>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ exclk_sc16is752: sc16is752 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+ };
+};
+
&i2c0 {
status = "okay";
@@ -225,6 +222,12 @@
bias-pull-up;
};
+ pins_ssi: ssi {
+ function = "ssi";
+ groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d";
+ bias-disable;
+ };
+
pins_i2c0: i2c0 {
function = "i2c0";
groups = "i2c0-data";
diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
index 0727bc9..461efba 100644
--- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
+++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
@@ -31,42 +31,6 @@
};
};
- ssi0: spi-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- num-chipselects = <1>;
-
- mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
- miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
- sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
-
- status = "okay";
-
- spi-max-frequency = <50000000>;
-
- sc16is752: expander@0 {
- compatible = "nxp,sc16is752";
- reg = <0>; /* CE0 */
- spi-max-frequency = <4000000>;
-
- clocks = <&exclk_sc16is752>;
-
- interrupt-parent = <&gpb>;
- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- exclk_sc16is752: sc16is752 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
- };
- };
-
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";
@@ -90,7 +54,7 @@
&ost {
/* 1500 kHz for the system timer and clocksource */
- assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
+ assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};
@@ -101,6 +65,38 @@
pinctrl-0 = <&pins_uart1>;
};
+&ssi0 {
+ status = "okay";
+
+ num-cs = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_ssi0>;
+
+ sc16is752: expander@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>; /* CE0 */
+
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ spi-max-frequency = <4000000>;
+
+ clocks = <&exclk_sc16is752>;
+
+ interrupt-parent = <&gpb>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ exclk_sc16is752: sc16is752 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+ };
+};
+
&i2c0 {
status = "okay";
@@ -229,6 +225,12 @@
bias-pull-up;
};
+ pins_ssi0: ssi0 {
+ function = "ssi0";
+ groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
+ bias-disable;
+ };
+
pins_i2c0: i2c0 {
function = "i2c0";
groups = "i2c0-data";
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index 591692d..958a5ef 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -259,6 +259,25 @@
status = "disabled";
};
+ ssi: spi@...43000 {
+ compatible = "ingenic,x1000-spi";
+ reg = <0x10043000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <8>;
+
+ clocks = <&cgu X1000_CLK_SSI>;
+ clock-names = "spi";
+
+ dmas = <&pdma X1000_DMA_SSI0_RX 0xffffffff>,
+ <&pdma X1000_DMA_SSI0_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ status = "disabled";
+ };
+
i2c0: i2c-controller@...50000 {
compatible = "ingenic,x1000-i2c";
reg = <0x10050000 0x1000>;
@@ -304,6 +323,7 @@
pdma: dma-controller@...20000 {
compatible = "ingenic,x1000-dma";
reg = <0x13420000 0x400>, <0x13421000 0x40>;
+
#dma-cells = <2>;
interrupt-parent = <&intc>;
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index ffe6073..231c72a 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -241,6 +241,44 @@
status = "disabled";
};
+ ssi0: spi@...43000 {
+ compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
+ reg = <0x10043000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <9>;
+
+ clocks = <&cgu X1830_CLK_SSI0>;
+ clock-names = "spi";
+
+ dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>,
+ <&pdma X1830_DMA_SSI0_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ status = "disabled";
+ };
+
+ ssi1: spi@...44000 {
+ compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
+ reg = <0x10044000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <8>;
+
+ clocks = <&cgu X1830_CLK_SSI1>;
+ clock-names = "spi";
+
+ dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>,
+ <&pdma X1830_DMA_SSI1_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ status = "disabled";
+ };
+
i2c0: i2c-controller@...50000 {
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
reg = <0x10050000 0x1000>;
@@ -295,6 +333,7 @@
pdma: dma-controller@...20000 {
compatible = "ingenic,x1830-dma";
reg = <0x13420000 0x400>, <0x13421000 0x40>;
+
#dma-cells = <2>;
interrupt-parent = <&intc>;
--
2.7.4
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