linux-kernel - Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles

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Message-ID: <d9663aa1-e574-f12f-a330-79d984af107e@alliedtelesis.co.nz>
Date:   Thu, 12 May 2022 00:38:56 +0000
From:   Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To:     Andrew Lunn <andrew@...n.ch>
CC:     "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "will@...nel.org" <will@...nel.org>,
        "gregory.clement@...tlin.com" <gregory.clement@...tlin.com>,
        "sebastian.hesselbarth@...il.com" <sebastian.hesselbarth@...il.com>,
        "kostap@...vell.com" <kostap@...vell.com>,
        "robert.marko@...tura.hr" <robert.marko@...tura.hr>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X
 compatibles


On 12/05/22 12:27, Andrew Lunn wrote:
> On Wed, May 11, 2022 at 11:14:25PM +0000, Chris Packham wrote:
>> On 12/05/22 05:02, Andrew Lunn wrote:
>>> On Wed, May 11, 2022 at 11:10:00AM +1200, Chris Packham wrote:
>>>> Describe the compatible properties for the Marvell Alleycat5/5X switches
>>>> with integrated CPUs.
>>>>
>>>> Alleycat5:
>>>> * 98DX2538: 24x1G + 2x10G + 2x10G Stack
>>>> * 98DX2535: 24x1G + 4x1G Stack
>>>> * 98DX2532: 8x1G + 2x10G + 2x1G Stack
>>>> * 98DX2531: 8x1G + 4x1G Stack
>>>> * 98DX2528: 24x1G + 2x10G + 2x10G Stack
>>>> * 98DX2525: 24x1G + 4x1G Stack
>>>> * 98DX2522: 8x1G + 2x10G + 2x1G Stack
>>>> * 98DX2521: 8x1G + 4x1G Stack
>>>> * 98DX2518: 24x1G + 2x10G + 2x10G Stack
>>>> * 98DX2515: 24x1G + 4x1G Stack
>>>> * 98DX2512: 8x1G + 2x10G + 2x1G Stack
>>>> * 98DX2511: 8x1G + 4x1G Stack
>>>>
>>>> Alleycat5X:
>>>> * 98DX3500: 24x1G + 6x25G
>>>> * 98DX3501: 16x1G + 6x10G
>>>> * 98DX3510: 48x1G + 6x25G
>>>> * 98DX3520: 24x2.5G + 6x25G
>>>> * 98DX3530: 48x2.5G + 6x25G
>>>> * 98DX3540: 12x5G/6x10G + 6x25G
>>>> * 98DX3550: 24x5G/12x10G + 6x25G
>>> Hi Chris
>>>
>>> When looking at this list, is it just the switch which changes, and
>>> everything else in the package stays the same?
>> CPU wise I've been told everything is identical. The differences are all
>> in the switch side.
> O.K. That helps a lot with this description.
>
>>> armada-98DX2538.dtsi which extends armada-98DX25xx.dtsi
>> There wouldn't be anything to add in 98DX2538 (at least not until we
>> have a proper switchdev driver).
> Does the switch/SoC have ID registers? For mv88e6xxx, the switch is
> identified by its ID registers, so we don't have switch specific
> compatible value in DT. Hopefully it is the same here. All we need to
> say is that there is a switch in the main .dtsi file, and the .dts
> file would then indicate which ports are actually used.

Yes there are registers that you can read to identify the specific chip.

It still might be useful to have a expected vs actual check as those ID 
values are determined by pin strapping resistors. It could also be used 
to validate the dts (e.g. port 20 would be invalid on a 98DX3501). But 
those are considerations for further down the track.

>     Andrew