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Date: Thu, 12 May 2022 08:43:06 +0200 From: Geert Uytterhoeven <geert@...ux-m68k.org> To: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> Cc: Linus Walleij <linus.walleij@...aro.org>, Thomas Gleixner <tglx@...utronix.de>, Marc Zyngier <maz@...nel.org>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Bartosz Golaszewski <brgl@...ev.pl>, Philipp Zabel <p.zabel@...gutronix.de>, "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, Linux-Renesas <linux-renesas-soc@...r.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>, Phil Edworthy <phil.edworthy@...esas.com>, Biju Das <biju.das.jz@...renesas.com>, Prabhakar <prabhakar.csengg@...il.com> Subject: Re: [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller Hi Prabhakar, On Wed, May 11, 2022 at 8:32 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> wrote: > Add DT bindings for the Renesas RZ/G2L Interrupt Controller. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> Thanks for the update! > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml > @@ -0,0 +1,134 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55) > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> > + - Geert Uytterhoeven <geert+renesas@...der.be> > + > +description: | > + IA55 performs various interrupt controls including synchronization for the external > + interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral > + interrupts output by each IP. And it notifies the interrupt to the GIC > + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts > + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts > + - NMI edge select (NMI is not treated as NMI exception and supports fall edge and > + stand-up edge detection interrupts) > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a07g044-irqc # RZ/G2L > + - const: renesas,rzg2l-irqc > + > + '#interrupt-cells': > + description: The first cell should contain interrupt number and the second cell > + is used to specify the flag. The important part is still missing: which interrupt number (the general description mentions 3 types)? I believe the answer is "external interrupt number". > + const: 2 > + > + Double blank line. > + '#address-cells': > + const: 0 Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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