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Message-Id: <20220513165050.500831-1-angelogioacchino.delregno@collabora.com>
Date: Fri, 13 May 2022 18:50:45 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: robh+dt@...nel.org
Cc: krzysztof.kozlowski+dt@...aro.org, matthias.bgg@...il.com,
mturquette@...libre.com, sboyd@...nel.org, p.zabel@...gutronix.de,
y.oudjana@...tonmail.com, angelogioacchino.delregno@...labora.com,
jason-jh.lin@...iatek.com, ck.hu@...iatek.com,
fparent@...libre.com, rex-bc.chen@...iatek.com,
tinghan.shen@...iatek.com, chun-jie.chen@...iatek.com,
weiyi.lu@...iatek.com, ikjn@...omium.org, miles.chen@...iatek.com,
sam.shih@...iatek.com, wenst@...omium.org,
bgolaszewski@...libre.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
konrad.dybcio@...ainline.org, marijn.suijten@...ainline.org,
martin.botka@...ainline.org, ~postmarketos/upstreaming@...ts.sr.ht,
phone-devel@...r.kernel.org, paul.bouchara@...ainline.org,
kernel@...labora.com
Subject: [PATCH 0/5] MediaTek Helio X10 MT6795 - Clock drivers
In an effort to give some love to the apparently forgotten MT6795 SoC,
I am upstreaming more components that are necessary to support platforms
powered by this one apart from a simple boot to serial console.
This (very big) series introduces system clock, multimedia clock drivers
(including resets) for this SoC.
Tested on a MT6795 Sony Xperia M5 (codename "Holly") smartphone.
AngeloGioacchino Del Regno (5):
dt-bindings: mediatek: Document MT6795 system controllers bindings
dt-bindings: clock: Add MediaTek Helio X10 MT6795 clock bindings
dt-bindings: reset: Add bindings for MT6795 Helio X10 reset
controllers
dt-bindings: arm: mediatek: Add clock driver bindings for MT6795
clk: mediatek: Add MediaTek Helio X10 MT6795 clock drivers
.../arm/mediatek/mediatek,infracfg.yaml | 2 +
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 1 +
.../arm/mediatek/mediatek,mt6795-clock.yaml | 67 ++
.../mediatek/mediatek,mt6795-sys-clock.yaml | 73 +++
.../arm/mediatek/mediatek,pericfg.yaml | 1 +
.../bindings/clock/mediatek,apmixedsys.yaml | 1 +
.../bindings/clock/mediatek,topckgen.yaml | 1 +
drivers/clk/mediatek/Kconfig | 37 ++
drivers/clk/mediatek/Makefile | 6 +
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 154 +++++
drivers/clk/mediatek/clk-mt6795-infracfg.c | 145 +++++
drivers/clk/mediatek/clk-mt6795-mfg.c | 47 ++
drivers/clk/mediatek/clk-mt6795-mm.c | 103 +++
drivers/clk/mediatek/clk-mt6795-pericfg.c | 157 +++++
drivers/clk/mediatek/clk-mt6795-topckgen.c | 607 ++++++++++++++++++
drivers/clk/mediatek/clk-mt6795-vdecsys.c | 52 ++
drivers/clk/mediatek/clk-mt6795-vencsys.c | 46 ++
include/dt-bindings/clock/mt6795-clk.h | 275 ++++++++
include/dt-bindings/reset/mt6795-resets.h | 50 ++
19 files changed, 1825 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml
create mode 100644 drivers/clk/mediatek/clk-mt6795-apmixedsys.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-infracfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-mfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-mm.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-pericfg.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-topckgen.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-vdecsys.c
create mode 100644 drivers/clk/mediatek/clk-mt6795-vencsys.c
create mode 100644 include/dt-bindings/clock/mt6795-clk.h
create mode 100644 include/dt-bindings/reset/mt6795-resets.h
--
2.35.1
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