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Message-ID: <CAJF2gTRmt5rWHNdtC9mh6ODFTBTz3XZz9Gq=NfAdJJpxPO3tBQ@mail.gmail.com>
Date: Fri, 13 May 2022 21:37:59 +0800
From: Guo Ren <guoren@...nel.org>
To: Anup Patel <anup@...infault.org>
Cc: Heiko Stuebner <heiko@...ech.de>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
linux-riscv <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
Wei Fu <wefu@...hat.com>, Atish Patra <atishp@...shpatra.org>,
Nick Kossifidis <mick@....forth.gr>,
Samuel Holland <samuel@...lland.org>,
Christoph Muellner <cmuellner@...ux.com>,
Philipp Tomsich <philipp.tomsich@...ll.eu>,
Rob Herring <robh+dt@...nel.org>, krzk+dt@...nel.org,
DTML <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 3/3] riscv: implement cache-management errata for
T-Head SoCs
Reviewed-by: Guo Ren <guoren@...nel.org>
On Thu, May 12, 2022 at 12:41 PM Anup Patel <anup@...infault.org> wrote:
>
> On Thu, May 12, 2022 at 3:11 AM Heiko Stuebner <heiko@...ech.de> wrote:
> >
> > The T-Head C906 and C910 implement a scheme for handling
> > cache operations different from the generic Zicbom extension.
> >
> > Add an errata for it next to the generic dma coherency ops.
> >
> > Tested-by: Samuel Holland <samuel@...lland.org>
> > Signed-off-by: Heiko Stuebner <heiko@...ech.de>
>
> Looks good to me.
>
> Reviewed-by: Anup Patel <anup@...infault.org>
>
> Regards,
> Anup
>
> > ---
> > arch/riscv/Kconfig.erratas | 10 ++++++
> > arch/riscv/errata/thead/errata.c | 5 +++
> > arch/riscv/include/asm/errata_list.h | 47 +++++++++++++++++++++++++---
> > 3 files changed, 58 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
> > index ebfcd5cc6eaf..213629bac5d7 100644
> > --- a/arch/riscv/Kconfig.erratas
> > +++ b/arch/riscv/Kconfig.erratas
> > @@ -54,4 +54,14 @@ config ERRATA_THEAD_PBMT
> >
> > If you don't know what to do here, say "Y".
> >
> > +config ERRATA_THEAD_CMO
> > + bool "Apply T-Head cache management errata"
> > + depends on ERRATA_THEAD && RISCV_ISA_ZICBOM
> > + default y
> > + help
> > + This will apply the cache management errata to handle the
> > + non-standard handling on non-coherent operations on T-Head SoCs.
> > +
> > + If you don't know what to do here, say "Y".
> > +
> > endmenu
> > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > index e5d75270b99c..9545f43d3504 100644
> > --- a/arch/riscv/errata/thead/errata.c
> > +++ b/arch/riscv/errata/thead/errata.c
> > @@ -33,6 +33,11 @@ static const struct errata_info errata_list[ERRATA_THEAD_NUMBER] = {
> > .stage = RISCV_ALTERNATIVES_EARLY_BOOT,
> > .check_func = errata_mt_check_func
> > },
> > + {
> > + .name = "cache-management",
> > + .stage = RISCV_ALTERNATIVES_BOOT,
> > + .check_func = errata_mt_check_func
> > + },
> > };
> >
> > static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid)
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index eebcd4415049..1da311fc5126 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -16,7 +16,8 @@
> >
> > #ifdef CONFIG_ERRATA_THEAD
> > #define ERRATA_THEAD_PBMT 0
> > -#define ERRATA_THEAD_NUMBER 1
> > +#define ERRATA_THEAD_CMO 1
> > +#define ERRATA_THEAD_NUMBER 2
> > #endif
> >
> > #define CPUFEATURE_SVPBMT 0
> > @@ -111,8 +112,37 @@ asm volatile(ALTERNATIVE( \
> > #define CBO_CLEAN_A0 ".long 0x25200F"
> > #define CBO_FLUSH_A0 ".long 0x05200F"
> >
> > +/*
> > + * dcache.ipa rs1 (invalidate, physical address)
> > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > + * 0000001 01010 rs1 000 00000 0001011
> > + * dache.iva rs1 (invalida, virtual address)
> > + * 0000001 00110 rs1 000 00000 0001011
> > + *
> > + * dcache.cpa rs1 (clean, physical address)
> > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > + * 0000001 01001 rs1 000 00000 0001011
> > + * dcache.cva rs1 (clean, virtual address)
> > + * 0000001 00100 rs1 000 00000 0001011
> > + *
> > + * dcache.cipa rs1 (clean then invalidate, physical address)
> > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > + * 0000001 01011 rs1 000 00000 0001011
> > + * dcache.civa rs1 (... virtual address)
> > + * 0000001 00111 rs1 000 00000 0001011
> > + *
> > + * sync.s (make sure all cache operations finished)
> > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > + * 0000000 11001 00000 000 00000 0001011
> > + */
> > +#define THEAD_INVAL_A0 ".long 0x0265000b"
> > +#define THEAD_CLEAN_A0 ".long 0x0245000b"
> > +#define THEAD_FLUSH_A0 ".long 0x0275000b"
> > +#define THEAD_SYNC_S ".long 0x0190000b"
> > +
> > #define ALT_CMO_OP(_op, _start, _size, _cachesize) \
> > -asm volatile(ALTERNATIVE( \
> > +asm volatile(ALTERNATIVE_2( \
> > + "nop\n\t" \
> > "nop\n\t" \
> > "nop\n\t" \
> > "nop\n\t" \
> > @@ -124,8 +154,17 @@ asm volatile(ALTERNATIVE( \
> > CBO_##_op##_A0 "\n\t" \
> > "add a0, a0, %0\n\t" \
> > "2:\n\t" \
> > - "bltu a0, %2, 3b\n\t", 0, \
> > - CPUFEATURE_CMO, CONFIG_RISCV_ISA_ZICBOM) \
> > + "bltu a0, %2, 3b\n\t" \
> > + "nop", 0, CPUFEATURE_CMO, CONFIG_RISCV_ISA_ZICBOM, \
> > + "mv a0, %1\n\t" \
> > + "j 2f\n\t" \
> > + "3:\n\t" \
> > + THEAD_##_op##_A0 "\n\t" \
> > + "add a0, a0, %0\n\t" \
> > + "2:\n\t" \
> > + "bltu a0, %2, 3b\n\t" \
> > + THEAD_SYNC_S, THEAD_VENDOR_ID, \
> > + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \
> > : : "r"(_cachesize), \
> > "r"(ALIGN((_start), (_cachesize))), \
> > "r"(ALIGN((_start) + (_size), (_cachesize))))
> > --
> > 2.35.1
> >
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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